Method of manufacturing a single transistor non-volatile, electrically alterable semiconductor memory device

Claim 1

A method of making an electrically programmable and erasable memory device comprising the steps of: defining a substrate; growing a first layer of dielectric material over said substrate; depositing a layer of polysilicon or amorphous silicon over said first layer; covering said layer of silicon with a protective material; annealing said layer of silicon to form. recrystallized silicon; removing a portion of said protective material to define a floating gate region; growing masking oxide on said floating gate region; removing the remainder of said protective material and the recrystallized silicon thereunder; depositing a second layer of dielectric material silicon dioxide over said floating gate and said substrate; patterning and forming a control gate; and defining a drain and a source region in said substrate.

Claim 2

A method of making an electrically programmable and erasable memory device comprising the steps of: defining a substrate; growing a first layer of dielectric material over said substrate; depositing a layer of polysilicon or amorphous silicon over said first layer; covering said layer of silicon with a protective material; annealing said layer of silicon to form. recrystallized silicon; removing a portion of said protective material to define a floating gate region; growing masking oxide on said floating gate region; removing the remainder of said protective material and the recrystallized silicon thereunder; depositing a second layer of dielectric material silicon dioxide over said floating gate and said substrate; patterning and forming a control gate; and defining a drain and a source region in said substrate.

Claim 7

A method of making a field isolation in a semiconductor integrated circuit device comprising the steps of: defining a substrate; growing a first layer of dielectric material over said substrate; depositing a first layer of polysilicon over said first layer of dielectric material; covering said first layer of polysilicon with a first protective layer; patterning and exposing an isolation region in said first protective layer with a masking material to form an exposed isolation region; removing the first protective layer, polysilicon layer from the exposed isolation region leaving a stack having sidewalls; removing the masking material; depositing a second protective layer; depositing a second polysilicon layer; removing the second polysilicon layer everywhere except around the sidewalls of the stack; converting the second polysilicon layer adjacent to said stack into silicon oxide spacer; implanting channel stop implant everywhere in the isolation region except where protected by the silicon oxide spacer; removing the second protective layer from areas not protected by the oxide spacer; removing the silicon oxide spacer; thermally growing field oxide adjacent said stack; and remove the remaining first protective layer and polysilicon layer.

Claim 8

A method of making a field isolation in a semiconductor integrated circuit device comprising the steps of: defining a substrate; growing a first layer of dielectric material over said substrate; depositing a first layer of polysilicon over said first layer of dielectric material; covering said first layer of polysilicon with a first protective layer; patterning and exposing an isolation region in said first protective layer with a masking material to form an exposed isolation region; removing the first protective layer, polysilicon layer from the exposed isolation region leaving a stack having sidewalls; removing the masking material; depositing a second protective layer; depositing a second polysilicon layer; removing the second polysilicon layer everywhere except around the sidewalls of the stack; converting the second polysilicon layer adjacent to said stack into silicon oxide spacer; implanting channel stop implant everywhere in the isolation region except where protected by the silicon oxide spacer; removing the second protective layer from areas not protected by the oxide spacer; removing the silicon oxide spacer; thermally growing field oxide adjacent said stack; and remove the remaining first protective layer and polysilicon layer.