Patent US5045491A successfully refreshed from Google Patents.
US5045491A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a nonvolatile memory array having cells with separate program and erase regions
Assignee: Texas Instruments Inc
•
Filing: 1990-09-28
•
Granted: 1991-09-03
•
Expires: 2010-09-28
Abstract
Abstract A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first and second sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor permits programming of the cells through the first tunnelling window only and erasing of the cells through the second tunnelling window only, or vice versa.
Inventors
- 👤 Manzur Gill
- 👤 Theodore D. Lindgren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:05
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
220 words
A method for fabricating a nonvolatile memory cell at a face of a semiconductor layer of a first conductivity-type, comprising: selectively doping said semiconductor layer with a dopant of a second conductivity-type opposite said first conductivity-type to create a source-column region including a source and to create a drain-column region including a drain, said drain spaced from said source by first and second sub-channels, said first sub-channel adjacent said drain; differentially growing thermal insulator regions over said source-column region and said drain-column region; forming a first conductive layer and a first insulator layer over said face; selectively etching said first conductive layer and said first insulator layer to define field-plate and a field-plate insulator over a part of said drain-column region and over said first sub-channel region; forming first and second tunnelling windows, said first tunnelling window formed over said source-column region on the side of said source-column region opposite said second sub-channel region, said second tunnelling window formed over said drain-column region on the side of said drain-column region opposite said first sub-channel region; forming a floating gate and a control gate, said floating gate formed over and insulated from said second sub-channel region, formed over said first tunnelling window and formed over said second tunnelling window, each said control gate formed over and insulated from said floating gate.
Claim 2
Independent Claim
220 words
A method for fabricating a nonvolatile memory cell at a face of a semiconductor layer of a first conductivity-type, comprising: selectively doping said semiconductor layer with a dopant of a second conductivity-type opposite said first conductivity-type to create a source-column region including a source and to create a drain-column region including a drain, said drain spaced from said source by first and second sub-channels, said first sub-channel adjacent said drain; differentially growing thermal insulator regions over said source-column region and said drain-column region; forming a first conductive layer and a first insulator layer over said face; selectively etching said first conductive layer and said first insulator layer to define field-plate and a field-plate insulator over a part of said drain-column region and over said first sub-channel region; forming first and second tunnelling windows, said first tunnelling window formed over said source-column region on the side of said source-column region opposite said second sub-channel region, said second tunnelling window formed over said drain-column region on the side of said drain-column region opposite said first sub-channel region; forming a floating gate and a control gate, said floating gate formed over and insulated from said second sub-channel region, formed over said first tunnelling window and formed over said second tunnelling window, each said control gate formed over and insulated from said floating gate.
Claim 3
Dependent Claim
13 words
The method of claim 1, including: forming an oxide-nitride-oxide layer on said floating-gate.
Claim 4
Dependent Claim
15 words
The method of claim 1, including: implanting dopant through said first and second tunnelling windows.
Claim 5
Independent Claim
225 words
A method for fabricating a nonvolatile memory array at a face of a semiconductor layer of a first conductivity-type, comprising: selectively doping said semiconductor layer with a dopant of a second conductivity-type opposite said first conductivity-type to create source-column lines and to create drain-column lines, each said drain-column line spaced from each said source-column line; differentially growing thermal insulator regions over said source-column lines and said drain-column lines; forming a first conductive layer and a first insulator layer over said face; selectively etching said first conductive layer and said first insulator layer to define field-plate lines and field-plate insulators, each said field-plate line and each said field plate insulator formed over a part of a said thermal insulator region over a said drain-column line and over first sub-channels adjacent said drain-column line; forming first and second tunnelling windows, said first tunnelling windows formed over said source-column lines on sides of said source-column lines opposite second sub-channels adjacent said first sub-channels, said second tunnelling windows formed over said drain-column lines on the sides of said drain-column lines opposite said first sub-channels; forming floating-gate strips over said face, said floating-strips over said first and second tunnelling windows over and insulated from said second sub-channels; forming a row-line/control-gate layer insulated from said floating-gate strips; forming row-lines/control-gates and floating gates from said row-line/control-gate layer and from said floating-gate strips.
Claim 6
Independent Claim
225 words
A method for fabricating a nonvolatile memory array at a face of a semiconductor layer of a first conductivity-type, comprising: selectively doping said semiconductor layer with a dopant of a second conductivity-type opposite said first conductivity-type to create source-column lines and to create drain-column lines, each said drain-column line spaced from each said source-column line; differentially growing thermal insulator regions over said source-column lines and said drain-column lines; forming a first conductive layer and a first insulator layer over said face; selectively etching said first conductive layer and said first insulator layer to define field-plate lines and field-plate insulators, each said field-plate line and each said field plate insulator formed over a part of a said thermal insulator region over a said drain-column line and over first sub-channels adjacent said drain-column line; forming first and second tunnelling windows, said first tunnelling windows formed over said source-column lines on sides of said source-column lines opposite second sub-channels adjacent said first sub-channels, said second tunnelling windows formed over said drain-column lines on the sides of said drain-column lines opposite said first sub-channels; forming floating-gate strips over said face, said floating-strips over said first and second tunnelling windows over and insulated from said second sub-channels; forming a row-line/control-gate layer insulated from said floating-gate strips; forming row-lines/control-gates and floating gates from said row-line/control-gate layer and from said floating-gate strips.
Claim 7
Dependent Claim
13 words
The method of claim 4, including: forming an oxide-nitride-oxide layer on said floating-gate.
Claim 8
Dependent Claim
15 words
The method of claim 4, including: implanting dopant through said first and second tunnelling windows.
References Cited (Backward Citations)
US4822750A
Cited
US4853895A
Cited
US4980309A
Cited
US4924437A
Cited
US4833096A
Cited
US4994403A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |