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Patent US5045913A successfully refreshed from Google Patents.
US5045913A
Expired / Lapsed
US
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Bit stack compatible input/output circuits
Assignee: International Business Machines Corp
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Filing: 1990-10-04
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Granted: 1991-09-03
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Expires: 2010-10-04
Abstract
Abstract In accordance with the teachings of this invention a method for positioning components of input/output circuits is provided. These components are positioned on a semiconductor substrate. The semiconductor substrate includes other than input/output circuits. Each input/output circuit is provided for processing a single bit of information within a data word containing multiple bits. The method includes the step of (1) dividing each input/output circuit into groups containing similar functional subcomponents; (2) forming a vertical column of subcomponents for each input/output circuit and connecting these subcomponents to perform the function; (3) placing said columns in adjacency to form a plurality of columns with like subcomponents immediately adjacent to each other forming row groups of said like subcomponents; and (4) forming guard rings around the subcomponent row groups if required. Also in accordance with this invention, a group of input/output circuits is provided. The group is positioned on an integrated circuit substrate that contains other than input/output circuits. The input/output circuits group includes a plurality of columns of circuitry component where each column represents all of the input/output circuit components for processing a single bit of information in a group of bits, a plurality of rows positioned across the columns containing like devices among said input/output circuits, and at least one guard ring containing at least one of the plurality of rows.
Inventors
- 👤 Robert P. Masleid
- 👤 Parsotam T. Patel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:38
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
75 words
A group of input/output circuits on an integrated circuit semiconductor substrate containing other circuits, said input/output circuits comprising: a plurality of columns of circuit components, each column representing all input/output circuit components for processing a single data bit in a group of bits; a plurality of rows positioned across said columns, each row containing like devices among said input/output circuits; and at least one guard ring containing at least one of said plurality of rows.
Claim 2
Dependent Claim
75 words
A group of input/output circuits on an integrated circuit semiconductor substrate containing other circuits, said input/output circuits comprising: a plurality of columns of circuit components, each column representing all input/output circuit components for processing a single data bit in a group of bits; a plurality of rows positioned across said columns, each row containing like devices among said input/output circuits; and at least one guard ring containing at least one of said plurality of rows.
Claim 3
Dependent Claim
27 words
The group of input/output circuits according to claim 1 further including an electrostatic discharge protection circuit device positioned to provide protection for a complete row of devices.
Claim 4
Dependent Claim
36 words
The group of input/output circuits according to claim 1 wherein at least two adjacent rows include guard rings containing their respective rows therein and the at least two guard rings share a common guard ring area.
Claim 5
Dependent Claim
75 words
A group of input/output circuits on an integrated circuit semiconductor substrate containing other circuits, said input/output circuits comprising; a plurality of columns of circuit components, each column representing only input/output circuit components for processing a single data bit in a group of bits; a plurality of rows positioned across said columns, each row containing like devices among said input/output circuits; and at least one guard ring containing at least one of said plurality of rows.
Claim 6
Dependent Claim
75 words
A group of input/output circuits on an integrated circuit semiconductor substrate containing other circuits, said input/output circuits comprising; a plurality of columns of circuit components, each column representing only input/output circuit components for processing a single data bit in a group of bits; a plurality of rows positioned across said columns, each row containing like devices among said input/output circuits; and at least one guard ring containing at least one of said plurality of rows.
Claim 7
Dependent Claim
27 words
The group of input/output circuits according to claim 4 further including an electrostatic discharge protection circuit device positioned to provide protection for a complete row of devices.
Claim 8
Dependent Claim
36 words
The group of input/output circuits according to claim 4 wherein at least two adjacent rows include guard rings containing their respective rows therein and the at least two guard rings share a common guard ring area.
Claim 9
Dependent Claim
74 words
A group of input/output circuits on an integrated circuit semiconductor substrate containing other circuits, said input/output circuits comprising; a plurality of columns of circuit components, each column representing input/output circuit components for processing a single data bit in a group of bits; a plurality of rows positioned across said columns, each row containing like devices among said input/output circuits; and at least one guard ring containing at least one of said plurality of rows.
Claim 10
Dependent Claim
74 words
A group of input/output circuits on an integrated circuit semiconductor substrate containing other circuits, said input/output circuits comprising; a plurality of columns of circuit components, each column representing input/output circuit components for processing a single data bit in a group of bits; a plurality of rows positioned across said columns, each row containing like devices among said input/output circuits; and at least one guard ring containing at least one of said plurality of rows.
Claim 11
Dependent Claim
27 words
The group of input/output circuits according to claim 7 further including an electrostatic discharge protection circuit device positioned to provide protection for a complete row of devices.
Claim 12
Dependent Claim
36 words
The group of input/output circuits according to claim 7 wherein at least two adjacent rows include guard rings containing their respective rows therein and the at least two guard rings share a common guard ring area.
Claim 13
Dependent Claim
76 words
A group of input/output circuits on an integrated circuit semiconductor substrate containing other circuits, said input/output circuits comprising; a plurality of columns of circuit components, each column representing input/output circuit components for processing a single data bit in a group of bits; a plurality of rows positioned across said columns, each row containing devices of like function among said input/output circuits; and at least one guard ring containing at least one of said plurality of rows.
Claim 14
Dependent Claim
76 words
A group of input/output circuits on an integrated circuit semiconductor substrate containing other circuits, said input/output circuits comprising; a plurality of columns of circuit components, each column representing input/output circuit components for processing a single data bit in a group of bits; a plurality of rows positioned across said columns, each row containing devices of like function among said input/output circuits; and at least one guard ring containing at least one of said plurality of rows.
Claim 15
Dependent Claim
27 words
The group of input/output circuits according to claim 10 further including an electrostatic discharge protection circuit device positioned to provide protection for a complete row of devices.
Claim 16
Dependent Claim
36 words
The group of input/output circuits according to claim 10 wherein at least two adjacent rows include guard rings containing their respective rows therein and the at least two guard rings share a common guard ring area.
References Cited (Backward Citations)
US3798606A
Cited
US3999214A
Cited
US3968478A
Cited
US4006492A
Cited
EP0052828A2
Cited
JPS58137229A
Cited
US4766475A
Cited
EP0170268A2
Cited
JPS61144843A
Cited
JPS6212147A
Cited
US4731643A
Cited
US4746966A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |