US5051691A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Zero power dissipation laser fuse signature circuit for redundancy in vlsi design
Assignee: Samsung Semiconductor Inc
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Filing: 1990-09-13
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Granted: 1991-09-24
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Expires: 2010-09-13
Abstract
Abstract A laser fuse signature circuit for testing whether a fuse link in an IC has been disconnected includes a first series circuit connecting the power and ground pins and a second series circuit, including the fuse and a plurality of diode devices, connecting an input pin to a first node in the first series circuit. Transistors included in the first series circuit are connected so that the laser fuse signature circuit does not conduct current during normal operation or leakage current testing of the IC.
Inventors
- 👤 Chen Y. Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:56
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/50; G01R31/74
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
341 words
In an integrated circuit having input, power, and ground pins, where signals having an operating voltage level are applied to the input pin during normal operating conditions, a fuse signature circuit for testing whether a fuse-link connecting a selected input pin to other circuitry on the integrated circuit is connected or disconnected, where a test signal having a test voltage level greater than the operating voltage level is applied to the selected input pin during fuse signature testing, said circuit for fuse signature testing comprising: a first transistor, of a first conductivity type, having first, second, and control terminals, with its first and control terminals coupled to the power pin and its second terminal coupled to a first node; a second transistor, of a second conductivity type, having first, second, and control terminals, with its first terminal coupled to said first node and its control terminal coupled to the power pin; a third transistor, of the first conductivity type, having a first terminal coupled to the second terminal of said second transistor, its control terminal coupled to the power pin, and its second terminal coupled to the ground pin, where said first, second, and third transistors serially connect power and ground pins; a series diode circuit, comprising at least one diode connected transistor of the first conductivity type, said series diode circuit serially connecting the fuse to said first node to reduce the voltage level applied to the input pin by the sum of the threshold voltages of said diode connected transistors included in said series diode circuit and with the magnitude of said sum sufficient to prevent said second transistor from turning on when a signal having the operating voltage level is applied to the input pin during normal operation and where said first and third transistors are turned off so that no current flows through said circuit for testing when the power and ground pins are grounded and a voltage signal is applied to the input pin to test the integrated circuit for a short circuit or leakage current.
Claim 2
Dependent Claim
341 words
In an integrated circuit having input, power, and ground pins, where signals having an operating voltage level are applied to the input pin during normal operating conditions, a fuse signature circuit for testing whether a fuse-link connecting a selected input pin to other circuitry on the integrated circuit is connected or disconnected, where a test signal having a test voltage level greater than the operating voltage level is applied to the selected input pin during fuse signature testing, said circuit for fuse signature testing comprising: a first transistor, of a first conductivity type, having first, second, and control terminals, with its first and control terminals coupled to the power pin and its second terminal coupled to a first node; a second transistor, of a second conductivity type, having first, second, and control terminals, with its first terminal coupled to said first node and its control terminal coupled to the power pin; a third transistor, of the first conductivity type, having a first terminal coupled to the second terminal of said second transistor, its control terminal coupled to the power pin, and its second terminal coupled to the ground pin, where said first, second, and third transistors serially connect power and ground pins; a series diode circuit, comprising at least one diode connected transistor of the first conductivity type, said series diode circuit serially connecting the fuse to said first node to reduce the voltage level applied to the input pin by the sum of the threshold voltages of said diode connected transistors included in said series diode circuit and with the magnitude of said sum sufficient to prevent said second transistor from turning on when a signal having the operating voltage level is applied to the input pin during normal operation and where said first and third transistors are turned off so that no current flows through said circuit for testing when the power and ground pins are grounded and a voltage signal is applied to the input pin to test the integrated circuit for a short circuit or leakage current.
Claim 3
Dependent Claim
36 words
The fuse signature circuit of claim 1 wherein: said first and third transistors are NMOS transistors and said second transistor is a PMOS transistor and said power pin is biased to a positive power supply voltage.
Claim 4
Dependent Claim
36 words
The fuse signature circuit of claim 1 wherein: said first and third transistors are PMOS transistors and said second transistor is an NMOS transistor and said power pin is biased to a negative power supply voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-23 | 1995-03-25 | 1995-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-23 | 1999-03-25 | 1999-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-23 | 2003-03-25 | 2003-09-24 | $7700.00 | Window Closed / Lapsed |