Method for forming a multilevel interconnect structure on a semiconductor wafer

Claim 1

A method for forming a multilevel interconnect structure on a semiconductor wafer, wherein the interconnect structure includes a Metal level having inwardly protruding contact vias leading to underlying electrically conductive areas and outwardly protruding pillars leading to an overlying conductive layer, the method comprising the following steps: selectively fabricating a wafer by depositing and patterning different conductive and insulating layers, and by doping, to begin producing electronic devices and desired integrated circuits on the wafer; the wafer being fabricated to include exposed electrically conductive areas; applying a first dielectric layer on the wafer; etching the dielectric to form a poly-metal dielectric layer having grooves corresponding to a first layer of conduction strips, the grooves being intersected by contact holes in communication with underlying electrically conductive areas on the wafer; depositing a layer of tungsten on the wafer to both fill the grooves and contact holes and cover the remaining surface areas of the poly-metal dielectric layer to a common substantially planar surface; and etching back the tungsten to the poly-metal dielectric layer while forming protruding integral pillars at locations corresponding to about the filled grooves as required in a Metal level.

Claim 2

A method for forming a multilevel interconnect structure on a semiconductor wafer, wherein the interconnect structure includes a Metal level having inwardly protruding contact vias leading to underlying electrically conductive areas and outwardly protruding pillars leading to an overlying conductive layer, the method comprising the following steps: selectively fabricating a wafer by depositing and patterning different conductive and insulating layers, and by doping, to begin producing electronic devices and desired integrated circuits on the wafer; the wafer being fabricated to include exposed electrically conductive areas; applying a first dielectric layer on the wafer; etching the dielectric to form a poly-metal dielectric layer having grooves corresponding to a first layer of conduction strips, the grooves being intersected by contact holes in communication with underlying electrically conductive areas on the wafer; depositing a layer of tungsten on the wafer to both fill the grooves and contact holes and cover the remaining surface areas of the poly-metal dielectric layer to a common substantially planar surface; and etching back the tungsten to the poly-metal dielectric layer while forming protruding integral pillars at locations corresponding to about the filled grooves as required in a Metal level.

Claim 11

A method for forming a multilevel interconnect structure on a semiconductor wafer, wherein the interconnect structure includes a Metal level having inwardly protruding contact vias leading to underlying electrically conductive areas and outwardly protruding pillars leading to an overlying conductive layer, the method comprising the following steps: selectively fabricating a wafer by depositing and patterning different conductive and insulating layers, and by doping, to begin producing electronic devices and desired integrated circuits on the wafer; the wafer being fabricated to include exposed electrically conductive areas; applying a dielectric layer on the wafer; removing portions of the dielectric layer to form a poly-metal dielectric layer having grooves corresponding to a layer of conduction strips, the grooves being intersected by contact holes in communication with underlying electrically conductive areas on the wafer; applying a metal layer on the wafer to fill both the grooves and contact holes and also to cover the remaining surface areas of the poly-metal dielectric layer to begin definition of a Metal level; and removing portions of the metal layer to the depth of the poly-metal dielectric layer, leaving pillars protruding integrally from conduction strips and contacts in the Metal level.

Claim 12

A method for forming a multilevel interconnect structure on a semiconductor wafer, wherein the interconnect structure includes a Metal level having inwardly protruding contact vias leading to underlying electrically conductive areas and outwardly protruding pillars leading to an overlying conductive layer, the method comprising the following steps: selectively fabricating a wafer by depositing and patterning different conductive and insulating layers, and by doping, to begin producing electronic devices and desired integrated circuits on the wafer; the wafer being fabricated to include exposed electrically conductive areas; applying a dielectric layer on the wafer; removing portions of the dielectric layer to form a poly-metal dielectric layer having grooves corresponding to a layer of conduction strips, the grooves being intersected by contact holes in communication with underlying electrically conductive areas on the wafer; applying a metal layer on the wafer to fill both the grooves and contact holes and also to cover the remaining surface areas of the poly-metal dielectric layer to begin definition of a Metal level; and removing portions of the metal layer to the depth of the poly-metal dielectric layer, leaving pillars protruding integrally from conduction strips and contacts in the Metal level.