Patent US5057449A successfully refreshed from Google Patents.
US5057449A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for creating two thicknesses of gate oxide within a dynamic random access memory
Assignee: Micron Technology Inc
•
Filing: 1990-03-26
•
Granted: 1991-10-15
•
Expires: 2010-03-26
Abstract
Abstract A process for creating two thicknesses or gate oxide within a dynamic random memory. The process begins by thermally growing a first layer of gate oxide on a silicon substrate. This first layer is then masked with photoresist in regions where cell access transistors will ultimately be fabricated. All oxide that is not masked is then removed with an oxide etch. After the photoresist is stripped, a second layer of gate oxide is thermally grown on the substrate. The resultant oxided layer, which comprises multiple-thickness components, is used as a pad oxide layer during a conventional LOCOS operation. Peripheral driver transistors are construction on top of a thin layer of gate oxide so as to optimize their performance, whereas, cell access transistors are constructed on top of a thicker layer of gate oxide so as to minimize row line capacitance. A net increase in row line access speed is thus obtained.
Inventors
- 👤 Tyler A. Lowrey
- 👤 Fernando Gonzalez
- 👤 Joseph J. Karniewicz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:02
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038; H10P14/61; H10P14/6322; H10D64/01346; Y; Y10; Y10S; Y10S148/00; Y10S148/163
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
308 words
A process for creating dynamic random access memory circuitry on a silicon substrate, said circuitry having a first gate oxide layer, on top of which cell access transistor gates are fabricated, and a second gate oxide layer that is thinner than said first gate oxide layer, on top of which peripheral row line driver transistor gates are fabricated, said process comprising the following steps: (a) thermal oxidation of the substrate to create a first gate oxide layer on the upper surface of the substrate; (b) masking the first gate oxide layer with a first photoresist mask in regions where cell access transistors will ultimately be constructed; (c) removal of those portions of the first gate oxide layer that are not subjacent the first photoresist mask with a first oxide etch, thus exposing unoxidized regions of the silicon substrate; (d) stripping the first photoresist mask; (e) thermal growth of a second gate oxide layer in the unoxidized regions of the upper surface of the substrate; (f) blanket deposition of a silicon nitride layer on top of first and second gate oxide layers; (g) masking of the silicon nitride layer with a second photoresist mask in regions which will become future active areas; (h) removal of those portions of the silicon nitride layer that were not subjacent the second photoresist mask with a first nitride etch; (i) stripping of the second photoresist mask; (j) creation of field oxide regions by the thermally oxidizing regions of the upper surface of the substrate which are not covered by remnants of the silicon nitride layer; (k) removal of remnants of the silicon nitride layer with a second nitride etch; and (l) creation of DRAM cell access transistor gates on top of the first gate oxide layer remnants and creations of peripheral driver transistor gates on top of the second gate oxide layer remnants.
Claim 2
Dependent Claim
308 words
A process for creating dynamic random access memory circuitry on a silicon substrate, said circuitry having a first gate oxide layer, on top of which cell access transistor gates are fabricated, and a second gate oxide layer that is thinner than said first gate oxide layer, on top of which peripheral row line driver transistor gates are fabricated, said process comprising the following steps: (a) thermal oxidation of the substrate to create a first gate oxide layer on the upper surface of the substrate; (b) masking the first gate oxide layer with a first photoresist mask in regions where cell access transistors will ultimately be constructed; (c) removal of those portions of the first gate oxide layer that are not subjacent the first photoresist mask with a first oxide etch, thus exposing unoxidized regions of the silicon substrate; (d) stripping the first photoresist mask; (e) thermal growth of a second gate oxide layer in the unoxidized regions of the upper surface of the substrate; (f) blanket deposition of a silicon nitride layer on top of first and second gate oxide layers; (g) masking of the silicon nitride layer with a second photoresist mask in regions which will become future active areas; (h) removal of those portions of the silicon nitride layer that were not subjacent the second photoresist mask with a first nitride etch; (i) stripping of the second photoresist mask; (j) creation of field oxide regions by the thermally oxidizing regions of the upper surface of the substrate which are not covered by remnants of the silicon nitride layer; (k) removal of remnants of the silicon nitride layer with a second nitride etch; and (l) creation of DRAM cell access transistor gates on top of the first gate oxide layer remnants and creations of peripheral driver transistor gates on top of the second gate oxide layer remnants.
Claim 3
Dependent Claim
112 words
A process for creating a dynamic random access memory fabricated on a silicon substrate, consisting of a process for creating a dual-function silicon dioxide layer having first and second thicknesses, said first thickness being greater than said second thickness, said dual-function silicon dioxide layer being initially used for a stress-relief layer between the substrate and a silicon nitride layering during a LOCOS step creating field oxide regions, and subsequently used for gate oxide, constructing cell access transistor gates on top portions of said dual-function silicon dioxide layer of said first thickness, and constructing peripheral row line drive transistor gates on top portions of said dual-function silicon dioxide layer of said second thickness.
Claim 4
Dependent Claim
112 words
A process for creating a dynamic random access memory fabricated on a silicon substrate, consisting of a process for creating a dual-function silicon dioxide layer having first and second thicknesses, said first thickness being greater than said second thickness, said dual-function silicon dioxide layer being initially used for a stress-relief layer between the substrate and a silicon nitride layering during a LOCOS step creating field oxide regions, and subsequently used for gate oxide, constructing cell access transistor gates on top portions of said dual-function silicon dioxide layer of said first thickness, and constructing peripheral row line drive transistor gates on top portions of said dual-function silicon dioxide layer of said second thickness.
Claim 5
Dependent Claim
271 words
A process for creating a dynamic random access memory as described in claim 2 wherein the process for creating and constructing comprises the following steps: (a) thermal oxidation of the substrate to create a first silicon dioxide layer on the upper surface of the substrate; (b) masking the first gate oxide layer with a first photoresist mask in regions where cell access transistors will ultimately be constructed; (c) removal of those portions of the first silicon dioxide layer that are not subjacent the first photoresist mask with a first oxide etch, thus exposing unoxidized regions of the silicon substrate; (d) stripping the first photoresist mask; (e) thermal growth of a second silicon dioxide layer in the unoxidized regions of the upper surface of the substrate; (f) blanket deposition of a silicon nitride layer on top of first and second gate oxide layers; (g) masking of the silicon nitride layer with a second photoresist mask in regions which will become future active areas; (h) removal of those portions of the silicon nitride layer that were not subjacent the second photoresist mask with a first nitride etch; (i) stripping of the second photoresist mask; (j) creation of field oxide regions by the thermally oxidizing regions of the upper surface of the substrate which are not covered by remnants of the silicon nitride layer; (k) removal of remnants of the silicon nitride layer with a second nitride etch; and (l) creation of DRAM cell access transistor gates on top of portions of the first silicon dioxide layer and creation of peripheral driver transistor gates on top of portions of the second silicon dioxide layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |