Method of manufacturing a bi-mos device with a polycrystalline resistor

Claim 2

In a method of manufacturing a Bi-MOS semiconductor device having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising the steps of: forming a plurality of element isolation regions each thereof being formed by forming in said semiconductor substrate a first semiconductor region of the same type of conductivity as said semiconductor substrate and selectively forming a thick insulation layer on said first semiconductor region; forming a thin insulation layer on a plurality of device forming regions surrounded by said element isolation regions and then forming simultaneously openings for one of emitter region and collector lead-out region and an opening for buried contact; forming a polycrystalline silicon layer forming at least one of an emitter electrode and a collector electrode in said bipolar device, gate electrodes of said MOS devices, a low-resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices, and a high-resistivity portion formed by a high-resistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer by the same growing and processing operations; and diffusing an impurity from said polycrystalline silicon layer to form said emitter region together with a buried contact region or to form said collector lead-out region together with a buried contact region.

Claim 3

In a method of manufacturing A Bi-MOS semiconductor device including a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising the steps of: forming a plurality of element isolation regions each thereof being formed by forming in said semiconductor substrate a first semiconductor region of the same type of conductivity as said semiconductor substrate, forming a second semiconductor region of the same type of conductivity as said semiconductor substrate in a semiconductor layer formed on said semiconductor substrate surface and different in conductivity type from said semiconductor substrate such that said second semiconductor region has a bottom portion thereof contacted with said first semiconductor layer, and selectively forming a thick insulation layer on said second semiconductor region; forming a thin insulation layer on device forming regions surrounded by said element isolation regions and then forming simultaneously openings for one of emitter region and collector lead-out region and an opening for buried contact; forming a polycrystalline silicon layer forming at least one of an emitter electrode and a collector electrode in said bipolar device, gate electrodes of said MOS devices, a low-resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices and a high-resistivity portion formed by a high-resistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer by the same growing and processing operations; and diffusing an impurity from said polycrystalline silicon layer to form said emitter region together with a buried contact region or to form said collector lead-out region together with a buried contact region.

Claim 4

In a method of manufacturing A Bi-MOS semiconductor device including a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate, the improvement comprising the steps of: forming a plurality of element isolation regions each thereof being formed by forming in said semiconductor substrate a first semiconductor region of the same type of conductivity as said semiconductor substrate, forming a second semiconductor region of the same type of conductivity as said semiconductor substrate in a semiconductor layer formed on said semiconductor substrate surface and different in conductivity type from said semiconductor substrate such that said second semiconductor region has a bottom portion thereof contacted with said first semiconductor layer, and selectively forming a thick insulation layer on said second semiconductor region; forming a thin insulation layer on device forming regions surrounded by said element isolation regions and then forming simultaneously openings for one of emitter region and collector lead-out region and an opening for buried contact; forming a polycrystalline silicon layer forming at least one of an emitter electrode and a collector electrode in said bipolar device, gate electrodes of said MOS devices, a low-resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices and a high-resistivity portion formed by a high-resistivity polycrystalline silicon layer connected to said low-resistivity polycrystalline silicon layer by the same growing and processing operations; and diffusing an impurity from said polycrystalline silicon layer to form said emitter region together with a buried contact region or to form said collector lead-out region together with a buried contact region.

Claim 5

A method according to claim 1 wherein said emitter electrode connected to said emitter region is formed by using said polycrystalline silicon layer said collector electrode connected to said collector lead-out region is formed by using a metal layer.

Claim 6

A method according to claim 1, wherein after said step of diffusing an impurity from said polycrystalline silicon layer to a low-resistivity polycrystalline silicon layer formed by a buried contact from one of said MOS devices, a metal silicide layer consists from Ti, W, Mo, Pt, Co is formed in a self-aligning manner on diffusion layers forming source and drain regions of said MOS devices and base regions of said bipolar device in said Bi-MOS semiconductor device and said polycrystalline silicon layer excluding said high-resistivity region.