Partial random access memory

Claim 2

A partial random access memory comprising: a plurality of memory cells arrayed in matrix form; a plurality of pairs of bit lines extending in a column direction, each of said plurality of memory cells being coupled to corresponding one of said pairs of bit lines, memory cells in one row respectively connected to different pairs of bit lines; a plurality of word lines including a plurality of first and second word lines, one first word line and one second word line being paired in one row and arranged in a row direction, each of said plurality of memory cells in each row being connected to at least one of said first and second word lines; activating means, coupled to said plurality of word lines, for separately activating said first and second word lines, depending on an address signal supplied from an external circuit, therein independently selecting said first and second word lines and selectively activating only those memory cells in one row which are connected to the selected word line; and input/output means, coupled to said plurality of bit lines, for writing input data into corresponding memory cells and reading out output data from corresponding memory cells.

Claim 3

A partial random access memory as claimed in claim 1, wherein some of said memory cells arranged in one row are connected to corresponding one of said first word lines, and the remaining memory cells arranged in the same row are connected to corresponding one of said second word lines.

Claim 4

A partial random access memory as claimed in claim 1, wherein said plurality of memory cells include a plurality of first memory cells and a plurality of second memory cells, and wherein said first memory cells are connected to the corresponding first word lines, and said second memory cells are connected to the corresponding second word lines.

Claim 5

A partial random access memory as claimed in claim 3, wherein said plurality of memory cells include a plurality of third memory cells, which are connected to both the paired first and second word lines.

Claim 6

A partial random access memory as claimed in claim 1, wherein each of said input and output data includes first data bits and second data bits, and said pairs of bit lines comprises pairs of first bit lines and pairs of second bit lines, and wherein said input/output means comprises, first input/output means for writing said first input data bits through said pairs of first bit lines into said memory cells connected to said first word lines and for reading out said first data bits therefrom, and second input/output means for writing said second data bits through said pairs of second bit lines into said memory cells connected to said second word lines and for reading out said second data bits therefrom.

Claim 7

A partial random access memory as claimed in claim 5, wherein said plurality of memory cells include a plurality of third memory cells, each of which is connected to both the paired first and second word lines and to both the pair of first bit lines and the pair of second bit lines.

Claim 8

A partial random access memory as claimed in claim 6, wherein each of said third memory cells comprises flip-flop means, connected to said activating means, for storing data amounting to one bit, first transfer gate means for selectively connecting said flip-flop means to corresponding one pair of first bit lines, and second transfer gate means, connected to said activating means, for selectively connecting said flip-flop means to corresponding one pair of second bit lines.

Claim 9

A partial random access memory as claimed in claim 7, wherein the pair of first bit lines and the pair of second bit lines with respect to said third memory cells transfer the same data bit.

Claim 10

A partial random access memory as claimed 7, wherein said flip-flop means comprises two complementary metal oxide semiconductor transistors, and each of said first and second transfer gate means comprises two N-channel metal oxide semiconductor transistor.

Claim 11

A partial random access memory as claimed in claim 5, wherein said first input/output means comprises a first port through which said first data bits to be input or output pass, and said second input/output means comprises a second port through with said second data bits to be input or output pass.

Claim 12

A partial random access memory as claimed in claim 1, wherein said activating means comprises first address decoding means for decoding said address signal to activate said first word lines, and second address decoding means for decoding said address signal to activate said second word lines with a timing different from a timing for said first address decoding means.

Claim 13

A partial random access memory as claimed in claim 1, wherein said plurality of memory cells include a plurality of first memory cells, a plurality of second memory cells, and a plurality of third memory cells, wherein said first memory cells are connected to the corresponding first word lines, and said second memory cells are connected to the corresponding second word lines, and wherein said third memory cells are connected to both the corresponding first and second word lines, and said arrangement of memory cells in one row includes said first, second and third memory cells.

Claim 14

A partial random access memory as claimed in claim 12, wherein in one row, said first memory cells are successively arranged, said second memory cells are successively arranged, and said third memory cells are successively arranged.

Claim 15

A partial random access memory as claimed in claim 12, wherein said first, second and third memory cells are repetitively arranged in this order one by one in one row.

Claim 16

A partial random access memory as claimed in claim 1, wherein said plurality of word lines include a plurality of third word lines extending from said activating means, and each of said third word lines is activated separately from said first and second word lines by said activating means, and wherein said plurality of memory cells include memory cells connected to said third word lines, said memory cells connected to one of said word lines amount to said input or output data.

Claim 17

A partial random access memory as claimed in claim 15, wherein said activating means comprises means for activating said third word lines separately from said first and second word lines.

Claim 18

A partial random access memory as claimed in claim 1, wherein each of said memory cells comprises flip-flop means for storing data amounting to one bit, and transfer gate means, connected to said activating means, for selectively connecting said flip-flop means to corresponding one pair of bit lines.

Claim 19

A partial random access memory as claimed in claim 1, wherein said partial random access memory is a static random access memory.

Claim 20

A partial random access memory as claimed in claim 1, wherein said partial random access memory is of the master slice type.

Claim 21

A partial random access memory comprising: a plurality of memory cells arrayed in matrix form, said plurality of memory cells include a plurality of first memory cells, a plurality of second memory cells, and a plurality of third memory cells; a plurality of pairs of bit lines extending in a column direction, each of said plurality of memory cells being coupled to corresponding one of said pairs of bit lines; a plurality of word lines including a plurality of first and second word lines, one first word line and one second word line being paired in one row and arranged in a row direction, each of said plurality of memory cells in each row being connected to at least one of said first and second word lines, said first memory cells are connected to the corresponding first word lines, said second memory cells are connected to the corresponding second word lines and said third memory cells connected to both the paired first and second word lines; activating means, coupled to said plurality of word lines, for separately activating said first and second word lines, depending on an address signal supplied from an external circuit, therein independently selecting said first and second word lines and selectively activating only those memory cells in one row which are connected to the selected word line; and input/output means, coupled to said plurality of bit lines, for writing input data into corresponding memory cells and reading out output data from corresponding memory cells.

Claim 22

A partial random access memory comprising: a plurality of memory cells arrayed in matrix form, said plurality of memory cells include a plurality of first memory cells, a plurality of second memory cells, and a plurality of third memory cells; a plurality of pairs of bit lines extending in a column direction, each of said plurality of memory cells being coupled to corresponding one of said pairs of bit lines; a plurality of word lines including a plurality of first and second word lines, one first word line and one second word line being paired in one row and arranged in a row direction, each of said plurality of memory cells in each row being connected to at least one of said first and second word lines, said first memory cells are connected to the corresponding first word lines, said second memory cells are connected to the corresponding second word lines and said third memory cells connected to both the paired first and second word lines; activating means, coupled to said plurality of word lines, for separately activating said first and second word lines, depending on an address signal supplied from an external circuit, therein independently selecting said first and second word lines and selectively activating only those memory cells in one row which are connected to the selected word line; and input/output means, coupled to said plurality of bit lines, for writing input data into corresponding memory cells and reading out output data from corresponding memory cells.