Fabrication of contact hole using an etch barrier layer

Claim 1

A method for forming a contact hole by utilizing an etch barrier layer in a semiconductor device, the method comprising the steps of: forming MOSFETs on a silicon substrate, each MOSFET having a field oxide film formed on the silicon substrate, a gate electrode formed on the field oxide film and a diffusion region formed into the silicon substrate between the field oxide films with the diffusion region being used as a source electrode or a drain electrode; depositing a first insulating film on the entire surface; forming conductive material layers on each portion of the first insulating film positioned on the gate electrodes of each MOSFET by a mask patterning process of the conductive material layer; depositing a second insulating film on the entire surface to insulate the conductive material layers from each other; forming an etch barrier layer on the second insulating film; depositing a third insulating film on the entire surface of the etch barrier layer and then flowing the same; forming a contact mask pattern for contact hole on the third insulating film positioned over the source electrode by utilizing a photoresistive layer as a contact mask; and performing a rounding process of a portion of the third insulating film by isotropically etching a portion of the third insulating film along the contact mask pattern; and, forming a contact hole by anisotropically etching a portion of the rounded third insulating film, a portion of the etch barrier layer, a portion of the second insulating film and a portion of the first insulating film, thereby preventing the second insulating film from being etched when the rounding process of a portion of the third insulating is performed by isotropically etching a portion of the third insulating film.

Claim 2

A method for forming a contact hole by utilizing an etch barrier layer in a semiconductor device, the method comprising the steps of: forming MOSFETs on a silicon substrate, each MOSFET having a field oxide film formed on the silicon substrate, a gate electrode formed on the field oxide film and a diffusion region formed into the silicon substrate between the field oxide films with the diffusion region being used as a source electrode or a drain electrode; depositing a first insulating film on the entire surface; forming conductive material layers on each portion of the first insulating film positioned on the gate electrodes of each MOSFET by a mask patterning process of the conductive material layer; depositing a second insulating film on the entire surface to insulate the conductive material layers from each other; forming an etch barrier layer on the second insulating film; depositing a third insulating film on the entire surface of the etch barrier layer and then flowing the same; forming a contact mask pattern for contact hole on the third insulating film positioned over the source electrode by utilizing a photoresistive layer as a contact mask; and performing a rounding process of a portion of the third insulating film by isotropically etching a portion of the third insulating film along the contact mask pattern; and, forming a contact hole by anisotropically etching a portion of the rounded third insulating film, a portion of the etch barrier layer, a portion of the second insulating film and a portion of the first insulating film, thereby preventing the second insulating film from being etched when the rounding process of a portion of the third insulating is performed by isotropically etching a portion of the third insulating film.

Claim 6

A method of forming a contact hole in a semiconductor device while maintaining intended electrical isolation of electrically conductive material layers, even in the presence of mask misalignment/excessive etching occurring during the fabrication process of the contact hole, said method comprising: forming field oxide films 2A, 2B spaced apart relative to each other on a silicon substrate 1; forming gate electrodes 3A, 3B on each of the field oxide films 2A, 2B by a gate mask patterning process; forming a diffusion region 4 by ion implantation into the portion of the silicon substrate between the spaced apart field oxide films 2A, 2B for use as either a source electrode or a drain electrode, thereby forming MOSFETs 30A, 30B; depositing a first insulating layer 5 on the entire surface of the resulting structure; depositing a conductive material layer 6 on the first insulating layer 5; etching away a portion of the conductive material layer deposited above the diffusion region by the mask patterning process of the conductive material layer 6 thereby forming conductive material layers 6A, 6B on a portion of the first insulating film; depositing a second insulating film 7 on the entire surface of the resulting structure; depositing an etch barrier layer 8 to a predetermined thickness on the second insulating film 7 to provide an isotropic etching barrier and an electrically insulating layer thereby protecting the conductive material layers 6A, 6B; depositing a third insulating film 9 on the entire resulting structure and the third insulating film 9 having an etching selectivity ratio which enables the third insulating film to be isotropically etched; flowing the third insulating film in order to smooth the surface of the structure; depositing a photoresistive layer on the entire resulting surface; etching a portion of the photoresistive layer 10 positioned over the diffusion region 4 to form a contact mask pattern 21; isotropically etching the third insulating film 9 to form a rounded opening 9A, 9B, having a bottom positioned over the diffusion region 4, in a portion of the third insulating film 9; and, forming a contact hole by anisotropically etching through the bottom of the rounded opening in the third insulating film, the second insulating film 7 and the first insulating film 5 by the contact mask patterning process to expose the surface of the diffusion region 4 such that an electrical short occurring between conductive material layers 6A,6B and a conductive material 11 deposited into the contact hole is prevented.

Claim 7

A method of forming a contact hole in a semiconductor device while maintaining intended electrical isolation of electrically conductive material layers, even in the presence of mask misalignment/excessive etching occurring during the fabrication process of the contact hole, said method comprising: forming field oxide films 2A, 2B spaced apart relative to each other on a silicon substrate 1; forming gate electrodes 3A, 3B on each of the field oxide films 2A, 2B by a gate mask patterning process; forming a diffusion region 4 by ion implantation into the portion of the silicon substrate between the spaced apart field oxide films 2A, 2B for use as either a source electrode or a drain electrode, thereby forming MOSFETs 30A, 30B; depositing a first insulating layer 5 on the entire surface of the resulting structure; depositing a conductive material layer 6 on the first insulating layer 5; etching away a portion of the conductive material layer deposited above the diffusion region by the mask patterning process of the conductive material layer 6 thereby forming conductive material layers 6A, 6B on a portion of the first insulating film; depositing a second insulating film 7 on the entire surface of the resulting structure; depositing an etch barrier layer 8 to a predetermined thickness on the second insulating film 7 to provide an isotropic etching barrier and an electrically insulating layer thereby protecting the conductive material layers 6A, 6B; depositing a third insulating film 9 on the entire resulting structure and the third insulating film 9 having an etching selectivity ratio which enables the third insulating film to be isotropically etched; flowing the third insulating film in order to smooth the surface of the structure; depositing a photoresistive layer on the entire resulting surface; etching a portion of the photoresistive layer 10 positioned over the diffusion region 4 to form a contact mask pattern 21; isotropically etching the third insulating film 9 to form a rounded opening 9A, 9B, having a bottom positioned over the diffusion region 4, in a portion of the third insulating film 9; and, forming a contact hole by anisotropically etching through the bottom of the rounded opening in the third insulating film, the second insulating film 7 and the first insulating film 5 by the contact mask patterning process to expose the surface of the diffusion region 4 such that an electrical short occurring between conductive material layers 6A,6B and a conductive material 11 deposited into the contact hole is prevented.