Bootstrapping level control circuit for word line signal producing circuit in a dram

Claim 2

A bootstrapping level control circuit for a word line signal producing circuit in a DRAM for completely supplying the potential of a word line signal source, through a word line signal transferring control circuit, to a memory cell array apparatus, when said word line signal transferring control circuit is enabled, said bootstrapping level control circuit comprises: a Vcc level detector provided with a first, second and third Vcc level detecting circuits for respectively detecting the potential level at said word line signal source, to thereby output respective detected signals detected therefrom, with each said first, second and third Vcc level detecting circuit being connected, in parallel, to said word line signal source and having each predetermined inverting level being different relative to each other; a logic combination circuit for logically combining a bootstrapping control signal φ2 with said respective detected signals detected by each said first, second and third Vcc level detecting circuit, said logic combination circuit including a NAND gate (G5) having two inputs connected to each other to receive said bootstrapping control signal φ2, and NAND gates (G6), (G7), and (G8) with one input of each said NAND gate (G6), (G7) and (G8) to receive said bootstrapping control signal φ2 and a remaining input of each said NAND gate (G6), (G7) and (G8) connected to each said first, second and third Vcc level detecting circuit, respectively, for receiving said respective detected signals of each said first, second and third Vcc level detecting circuit of said Vcc level detector, thereby outputting logically combined signals, respectively; an inverting circuit for delaying each said logically combined signals outputted from each said NAND gate (G5), (G6), (G7) and (G8) of the logic combination circuit, said inverting circuit including a plurality of NOT gates (G1), (G2), (G3) and (G4), respectively, connected to each said NAND gate (G5), (G6), (G7) and (G8) for inverting each said logically combined signals from said logic combination circuit, to thereby output an inverted signal for each said logically combined signal, respectively; and, a bootstrapping circuit including a bootstrapping capacitor, MOSFET capacitors (C2), (C3) and (C4), respectively, connected, in parallel, to a bootstrapping point, node (N1), for bootstrapping said bootstrapping point, node (N1), depending upon each said inverted signal, respectively, received from each said NOT gates (G1), (G2), (G3) and (G4) of the inverting circuit, thereby varying the bootstrapping efficiency of said bootstrapping level control circuit depending upon the potential level at said word line signal source detected by each said first, second and third Vcc level detecting circuit to prevent double bootstrapping effects from being occurred in said word line transferring control circuit.

Claim 3

The bootstrapping level control circuit of claim 1, wherein each of said first, second and third Vcc level detecting circuits comprises: a MOSFET (Q3) having a gate electrode and a drain electrode connected to each other and to said word line signal source, and a source electrode; a MOSFET (Q4) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q3), and a source electrode connected to a junction (P1); a MOSFET (Q5) having a gate electrode and a drain electrode connected to each other and to said junction (P1), and a source electrode; a MOSFET (Q6) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q5), and a source electrode connected to a junction (P2), with each said gate electrode of each said MOSFET (Q3), (Q4), (Q5) and (Q6) having a predetermined a width Wna, respectively; a MOSFET (Q7) having a gate electrode connected to said junction (P1), a drain electrode connected to said junction (P2), and a source electrode connected to a ground, with said gate electrode of said MOSFET (Q7) having a predetermined width Wnb such that, in use, said MOSFET (Q7) varies a potential level at said junction (P2) by varying the value of the on-resistance in accordance with a potential level of said junction (P1) according to the ratio of Wna to Wnb; and, a NOT gate (G9) having an input terminal connected to said junction (P2), and an output terminal connected to any one of said remaining inputs of said NAND gates (G6), (G7) and (G8), with said NOT gate (G9) having a predetermined inverting level, thereby alternatively inverting said potential level of said junction (P2) through said NOT gate (G9), either to a "high" level state or to a "low" level state, depending upon said predetermined inverting level of said NOT gate (G9).

Claim 4

The bootstrapping level control circuit of claim 2, wherein each said MOSFET (Q3), (Q4), (Q5), (Q6) and (Q7) is a N-channel MOSFET.

Claim 5

A bootstrapping level control circuit for a word line signal producing circuit in a DRAM for completely supplying the potential of a word line signal source, through a word line signal transferring control circuit, to a memory cell array apparatus, when said word line signal transferring control circuit is enabled, said bootstrapping level control circuit comprises: a Vcc level detector provided with a first, second and third Vcc level detecting circuits for respectively detecting the potential level at said word line signal source, to thereby output respective detected signals detected therefrom, with each of said first, second and third Vcc level detecting circuit comprising: a MOSFET (Q3) having a gate electrode and a drain electrode connected to each other and to said word line signal source, and a source electrode; a MOSFET (Q4) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q3), and a source electrode connected to a junction (P1); a MOSFET (Q5) having a gate electrode and a drain electrode connected to each other and to said junction (P1), and a source electrode; a MOSFET (Q6) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q5), and a source electrode connected to a junction (P2), with each said gate electrode of each said MOSFET (Q3), (Q4), (Q5) and (Q6) having a predetermined a width Wna, respectively; a MOSFET (Q7) having a gate electrode connected to said junction (P1), a drain electrode connected to said junction (P2), and a source electrode connected to a ground, with said gate electrode of said MOSFET (Q7) having a predetermined width Wnb such that, in use, said MOSFET (Q7) varies a potential level at said junction (P2) by varying the value of the on-resistance in accordance with a potential level of said junction (P1) according to the ratio of Wna to Wnb; and, a NOT gate (G9) having an input terminal connected to said junction (P2), and an output terminal connected to any one of said remaining inputs of said NAND gates (G6), (G7) and (G8), with said NOT gate (G9) having a predetermined inverting level, thereby alternatively inverting said potential level of said junction (P2) through said NOT gate (G9), either to a "high" level state or to a "low" level state, depending upon said predetermined inverting level of said NOT gate (G9); a logic combination circuit for logically combining a bootstrapping control signal φ2 with said respective detected signals detected by each said first, second and third Vcc level detecting circuit, said logic combination circuit including a NAND gate (G5) having two inputs connected to each other to receive said bootstrapping control signal φ2, and NAND gates (G6), (G7) and (G8) with one input of each said NAND gate (G6), (G7) and (G8) to receive said bootstrapping control signal φ2 and a remaining input of each said NAND gate (G6), (G7) and (G8) connected to each said first, second and third Vcc level detecting circuit, respectively, for receiving said respective detected signals of each said first, second and third Vcc level detecting circuit of said Vcc level detector, thereby outputting logically combined signals, respectively; an inverting circuit for delaying each said logically combined signals outputted from each said NAND gate (G5), (G6), (G7) and (G8) of the logic combination circuit, said inverting circuit including a plurality of NOT gates (G1), (G2), (G3) and (G4), respectively, connected to each said NAND gate (G5), (G6), (G7) and (G8) for inverting each said logically combined signals from said logic combination circuit, to thereby output an inverted signal for each said logically combined signal, respectively; and, a bootstrapping circuit including a bootstrapping capacitor, MOSFET capacitors (C2), (C3) and (C4), respectively, connected, in parallel, to a bootstrapping point, node (N1), for bootstrapping said bootstrapping point, node (N1), depending upon each said inverted signal, respectively, received from each said NOT gates (G1), (G2), (G3) and (G4) of the inverting circuit, thereby varying the bootstrapping efficiency of said bootstrapping level control circuit depending upon the potential level at said word line signal source detected by each said first, second and third Vcc level detecting circuit to prevent double bootstrapping effects from being occurred in said word line transferring control circuit.

Claim 6

A bootstrapping level control circuit for a word line signal producing circuit in a DRAM for completely supplying the potential of a word line signal source, through a word line signal transferring control circuit, to a memory cell array apparatus, when said word line signal transferring control circuit is enabled, said bootstrapping level control circuit comprises: a Vcc level detector provided with a first, second and third Vcc level detecting circuits for respectively detecting the potential level at said word line signal source, to thereby output respective detected signals detected therefrom, with each of said first, second and third Vcc level detecting circuit comprising: a MOSFET (Q3) having a gate electrode and a drain electrode connected to each other and to said word line signal source, and a source electrode; a MOSFET (Q4) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q3), and a source electrode connected to a junction (P1); a MOSFET (Q5) having a gate electrode and a drain electrode connected to each other and to said junction (P1), and a source electrode; a MOSFET (Q6) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q5), and a source electrode connected to a junction (P2), with each said gate electrode of each said MOSFET (Q3), (Q4), (Q5) and (Q6) having a predetermined a width Wna, respectively; a MOSFET (Q7) having a gate electrode connected to said junction (P1), a drain electrode connected to said junction (P2), and a source electrode connected to a ground, with said gate electrode of said MOSFET (Q7) having a predetermined width Wnb such that, in use, said MOSFET (Q7) varies a potential level at said junction (P2) by varying the value of the on-resistance in accordance with a potential level of said junction (P1) according to the ratio of Wna to Wnb; and, a NOT gate (G9) having an input terminal connected to said junction (P2), and an output terminal connected to any one of said remaining inputs of said NAND gates (G6), (G7) and (G8), with said NOT gate (G9) having a predetermined inverting level, thereby alternatively inverting said potential level of said junction (P2) through said NOT gate (G9), either to a "high" level state or to a "low" level state, depending upon said predetermined inverting level of said NOT gate (G9); a logic combination circuit for logically combining a bootstrapping control signal φ2 with said respective detected signals detected by each said first, second and third Vcc level detecting circuit, said logic combination circuit including a NAND gate (G5) having two inputs connected to each other to receive said bootstrapping control signal φ2, and NAND gates (G6), (G7) and (G8) with one input of each said NAND gate (G6), (G7) and (G8) to receive said bootstrapping control signal φ2 and a remaining input of each said NAND gate (G6), (G7) and (G8) connected to each said first, second and third Vcc level detecting circuit, respectively, for receiving said respective detected signals of each said first, second and third Vcc level detecting circuit of said Vcc level detector, thereby outputting logically combined signals, respectively; an inverting circuit for delaying each said logically combined signals outputted from each said NAND gate (G5), (G6), (G7) and (G8) of the logic combination circuit, said inverting circuit including a plurality of NOT gates (G1), (G2), (G3) and (G4), respectively, connected to each said NAND gate (G5), (G6), (G7) and (G8) for inverting each said logically combined signals from said logic combination circuit, to thereby output an inverted signal for each said logically combined signal, respectively; and, a bootstrapping circuit including a bootstrapping capacitor, MOSFET capacitors (C2), (C3) and (C4), respectively, connected, in parallel, to a bootstrapping point, node (N1), for bootstrapping said bootstrapping point, node (N1), depending upon each said inverted signal, respectively, received from each said NOT gates (G1), (G2), (G3) and (G4) of the inverting circuit, thereby varying the bootstrapping efficiency of said bootstrapping level control circuit depending upon the potential level at said word line signal source detected by each said first, second and third Vcc level detecting circuit to prevent double bootstrapping effects from being occurred in said word line transferring control circuit.

Claim 7

The bootstrapping level control circuit of claim 4, wherein each said MOSFET (Q3), (Q4), (Q5), (Q6) and (Q7) is a N-channel MOSFET.

Claim 8

A bootstrapping level control circuit for a word line signal producing circuit in a DRAM for completely supplying the potential of a word line signal source, through a word line signal transferring control circuit, to a memory cell array apparatus, when said word line signal transferring control circuit is enabled, said bootstrapping level control circuit comprises: a Vcc level detector provided with a first, second and third Vcc level detecting circuits for respectively detecting the potential level at said word line signal source, to thereby output respective detected signals detected therefrom, with each said first, second and third Vcc level detecting circuit being connected, in parallel, to said word line signal source and having each predetermined inverting level being different relative to each other; a logic combination circuit for logically combining a bootstrapping control signal φ2 with said respective detected signals detected by each said first, second and third Vcc level detecting circuit, respectively; an inverting circuit for delaying each said logically combined signals outputted from each said NAND gate (G5), (G6), (G7) and (G8) of the logic combination circuit, said inverting circuit including a plurality of NOT gates (G1), (G2), (G3) and (G4), respectively, connected to each said NAND gate (G5), (G6), (G7) and (G8) for inverting each said logically combined signals from said logic combination circuit, to thereby output an inverted signal for each said logically combined signal, respectively; and, a bootstrapping circuit including a bootstrapping capacitor, MOSFET capacitors (C2), (C3) and (C4), respectively, connected, in parallel, to a bootstrapping point, node (N1), for bootstrapping said bootstrapping point, node (N1), depending upon each said inverted signal, respectively, received from each said NOT gates (G1), (G2), (G3) and (G4) of the inverting circuit, thereby varying the bootstrapping efficiency of said bootstrapping level control circuit depending upon the potential level at said word line signal source detected by each said first, second and third Vcc level detecting circuit to prevent double bootstrapping effects from being occurred in said word line transferring control circuit.

Claim 9

A bootstrapping level control circuit for a word line signal producing circuit in a DRAM for completely supplying the potential of a word line signal source, through a word line signal transferring control circuit, to a memory cell array apparatus, when said word line signal transferring control circuit is enabled, said bootstrapping level control circuit comprises: a Vcc level detector provided with a first, second and third Vcc level detecting circuits for respectively detecting the potential level at said word line signal source, to thereby output respective detected signals detected therefrom, with each said first, second and third Vcc level detecting circuit being connected, in parallel, to said word line signal source and having each predetermined inverting level being different relative to each other; a logic combination circuit for logically combining a bootstrapping control signal φ2 with said respective detected signals detected by each said first, second and third Vcc level detecting circuit, respectively; an inverting circuit for delaying each said logically combined signals outputted from each said NAND gate (G5), (G6), (G7) and (G8) of the logic combination circuit, said inverting circuit including a plurality of NOT gates (G1), (G2), (G3) and (G4), respectively, connected to each said NAND gate (G5), (G6), (G7) and (G8) for inverting each said logically combined signals from said logic combination circuit, to thereby output an inverted signal for each said logically combined signal, respectively; and, a bootstrapping circuit including a bootstrapping capacitor, MOSFET capacitors (C2), (C3) and (C4), respectively, connected, in parallel, to a bootstrapping point, node (N1), for bootstrapping said bootstrapping point, node (N1), depending upon each said inverted signal, respectively, received from each said NOT gates (G1), (G2), (G3) and (G4) of the inverting circuit, thereby varying the bootstrapping efficiency of said bootstrapping level control circuit depending upon the potential level at said word line signal source detected by each said first, second and third Vcc level detecting circuit to prevent double bootstrapping effects from being occurred in said word line transferring control circuit.

Claim 10

The bootstrapping level control circuit of claim 6, wherein each of said first, second and third Vcc level detecting circuits comprises: a MOSFET (Q3) having a gate electrode and a drain electrode connected to each other and to said word line signal source, and a source electrode; a MOSFET (Q4) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q3), and a source electrode connected to a junction (P1); a MOSFET (Q5) having a gate electrode and a drain electrode connected to each other and to said junction (P1), and a source electrode; a MOSFET (Q6) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q5), and a source electrode connected to a junction (P2), with each said gate electrode of each said MOSFET (Q3), (Q4), (Q5) and (Q6) having a predetermined a width Wna, respectively; a MOSFET (Q7) having a gate electrode connected to said junction (P1), a drain electrode connected to said junction (P2), and a source electrode connected to a ground, with said gate electrode of said MOSFET (Q7) having a predetermined width Wnb such that, in use, said MOSFET (Q7) varies a potential level at said junction (P2) by varying the value of the on-resistance in accordance with a potential level of said junction (P1) according to the ratio of Wna to Wnb; and, a NOT gate (G9) having an input terminal connected to said junction (P2), and an output terminal connected to any one of said remaining inputs of said NAND gates (G6), (G7) and (G8), with said NOT gate (G9) having a predetermined inverting level, thereby alternatively inverting said potential level of said junction (P2) through said NOT gate (G9), either to a "high" level state or to a "low" level state, depending upon said predetermined inverting level of said NOT gate (G9).

Claim 11

The bootstrapping level control circuit of claim 7, wherein each said MOSFET (Q3), (Q4), (Q5), (Q6) and (Q7) is a N-channel MOSFET.

Claim 12

A bootstrapping level control circuit of claim 6, wherein said logic combination circuit includes said NAND gate (G5) having two inputs connected to each other to receive said bootstrapping control signal φ2, and each said NAND gate (G6), (G7) and (G8) with one input of each said NAND gate (G6), (G7) and (G8) to receive said bootstrapping control signal φ2 and the remaining input of each said NAND gate (G6), (G7) and (G8) connected to each said first, second and third Vcc level detecting circuit, respectively, for receiving said respective detected signals of each said first, second and third Vcc level detecting circuit of said Vcc level detector, thereby outputting logically combined signals, respectively.

Claim 13

A bootstrapping level control circuit for use in a word line signal producing circuit in a DRAM for detecting an existing potential level at a word line signal source and for providing variable bootstrapping efficiency according to said detected existing potential level at said word line signal source to supply sufficient supply voltage Vcc of said word line signal source to a memory cell array apparatus and to prevent double bootstrapping effects from occurring in a word line signal transferring control circuit, said bootstrapping level control circuit comprises: a Vcc level detector for detecting said existing potential level at said word line signal source, said Vcc level detector including a first, second and a third Vcc level detecting circuits with each said Vcc level detecting circuit having a predetermined inverting level, respectively, with each said predetermining inverting level of each said Vcc level detecting circuit being different relative to each other, with said first, second and third Vcc level detecting circuits of said Vcc level detector being connected, in parallel, to said word line signal source, respectively, such that, in use, each said Vcc level detecting circuit outputs a detected signal; a logic combination circuit for logically combining a bootstrapping control signal with each said detected signal detected by each said first, second and third Vcc level detecting circuit of said Vcc level detector, said logic combination circuit including a NAND gate (G5) having two inputs connected to each other with said connected inputs receiving, in use, said bootstrapping control signal, and NAND gates (G6), (G7) and (G8), with one input of each said NAND gate being connected to each other and to said inputs of said NAND gate (G5) to thereby receive, in use, said bootstrapping control signal, and a remaining input of each said NAND gate (G6), (G7) and (G8) connected to each said first, second and third Vcc level detecting circuit, respectively for receiving said detected signals of said Vcc level detecting circuits, respectively, such that, in use, each said NAND gate outputs a logically combined signal; an inverting circuit having NOT gates (G1), (G2), (G3) and (G4) for delaying, respectively, each said logically combined signal outputted from each said NAND gates (G5), (G6), (G7) and (G8) of said logic combination circuit to invert each said logically combined signal to form an inverted signal for each said logically combined signal received; and, a bootstrapping circuit for bootstrapping a bootstrapping point, node (N1), by receiving each said inverted signal, said bootstrapping circuit including a bootstrapping capacitor Cboost and MOSFET capacitors (C2), (C3) and (C4), with each said capacitor having a source, a drain and a gate electrode and with said source electrode and said drain electrode of each said capacitor being connected to each other and further connected to NOT gate (G1), (G2), (G3) and (G4) of said inverting circuit, respectively, and with said gate electrode of each said capacitor Cboost, (C2), (C3) and (C4), being connected, in parallel, to said bootstrapping point, node (N1), respectively, such that in use said bootstrapping point, node (N1), is bootstrapped depending upon said inverted signals outputted from said respective NOT gates (G1), (G2), (G3) and (G4) of said inverting circuit, thereby varying bootstrapping efficiency of said bootstrapping level control circuit depending upon said potential detected at said word line signal source.

Claim 14

A bootstrapping level control circuit for use in a word line signal producing circuit in a DRAM for detecting an existing potential level at a word line signal source and for providing variable bootstrapping efficiency according to said detected existing potential level at said word line signal source to supply sufficient supply voltage Vcc of said word line signal source to a memory cell array apparatus and to prevent double bootstrapping effects from occurring in a word line signal transferring control circuit, said bootstrapping level control circuit comprises: a Vcc level detector for detecting said existing potential level at said word line signal source, said Vcc level detector including a first, second and a third Vcc level detecting circuits with each said Vcc level detecting circuit having a predetermined inverting level, respectively, with each said predetermining inverting level of each said Vcc level detecting circuit being different relative to each other, with said first, second and third Vcc level detecting circuits of said Vcc level detector being connected, in parallel, to said word line signal source, respectively, such that, in use, each said Vcc level detecting circuit outputs a detected signal; a logic combination circuit for logically combining a bootstrapping control signal with each said detected signal detected by each said first, second and third Vcc level detecting circuit of said Vcc level detector, said logic combination circuit including a NAND gate (G5) having two inputs connected to each other with said connected inputs receiving, in use, said bootstrapping control signal, and NAND gates (G6), (G7) and (G8), with one input of each said NAND gate being connected to each other and to said inputs of said NAND gate (G5) to thereby receive, in use, said bootstrapping control signal, and a remaining input of each said NAND gate (G6), (G7) and (G8) connected to each said first, second and third Vcc level detecting circuit, respectively for receiving said detected signals of said Vcc level detecting circuits, respectively, such that, in use, each said NAND gate outputs a logically combined signal; an inverting circuit having NOT gates (G1), (G2), (G3) and (G4) for delaying, respectively, each said logically combined signal outputted from each said NAND gates (G5), (G6), (G7) and (G8) of said logic combination circuit to invert each said logically combined signal to form an inverted signal for each said logically combined signal received; and, a bootstrapping circuit for bootstrapping a bootstrapping point, node (N1), by receiving each said inverted signal, said bootstrapping circuit including a bootstrapping capacitor Cboost and MOSFET capacitors (C2), (C3) and (C4), with each said capacitor having a source, a drain and a gate electrode and with said source electrode and said drain electrode of each said capacitor being connected to each other and further connected to NOT gate (G1), (G2), (G3) and (G4) of said inverting circuit, respectively, and with said gate electrode of each said capacitor Cboost, (C2), (C3) and (C4), being connected, in parallel, to said bootstrapping point, node (N1), respectively, such that in use said bootstrapping point, node (N1), is bootstrapped depending upon said inverted signals outputted from said respective NOT gates (G1), (G2), (G3) and (G4) of said inverting circuit, thereby varying bootstrapping efficiency of said bootstrapping level control circuit depending upon said potential detected at said word line signal source.

Claim 15

The bootstrapping level control circuit of claim 10, wherein each of said first, second and third Vcc level detecting circuits comprises: a MOSFET (Q3) having a gate electrode and a drain electrode connected to each other and to said word line signal source, and a source electrode; a MOSFET (Q4) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q3), and a source electrode connected to a junction (P1); a MOSFET (Q5) having a gate electrode and a drain electrode connected to each other and to said junction (P1), and a source electrode; a MOSFET (Q6) having a gate electrode and a drain electrode connected to each other and to said source electrode of said MOSFET (Q5), and a source electrode connected to a junction (P2), with each said gate electrode of each said MOSFET (Q3), (Q4), (Q5) and (Q6) having a predetermined a width Wna, respectively; a MOSFET (Q7) having a gate electrode connected to said junction (P1), a drain electrode connected to said junction (P2), and a source electrode connected to a ground, with said gate electrode of said MOSFET (Q7) having a predetermined width Wnb such that, in use, said MOSFET (Q7) varies a potential level at said junction (P2) by varying the value of the on-resistance in accordance with a potential level of said junction (P1) according to the ratio of Wna to Wnb; and, a NOT gate (G9) having an input terminal connected to said junction (P2), and an output terminal connected to any one of said remaining inputs of said NAND gates (G6), (G7) and (G8), with said NOT gate (G9) having a predetermined inverting level, thereby alternatively inverting said potential level of said junction (P2) through said NOT gate (G9), either to a "high" level state or to a "low" level state, depending upon said predetermined inverting level of said NOT gate (G9).

Claim 16

The bootstrapping level control circuit of claim 11, wherein each said MOSFET (Q3), (Q4), (Q5), (Q6) and (Q7) is a N-channel MOSFET.