Method of making a bic memory cell having contact openings with straight sidewalls and sharp-edge rims

Claim 3

A method as claimed in claim 1 in which said step of providing the first opening comprises a step of opening the hole by an anisotropic etching process so that the first opening is defined by a straight side wall having a straight vertical cross section and extending perpendicularly to the surface of the substrate such that a sharp edge is defined at a rim of the first opening at the surface of the first insulating layer, and a step of blunting the sharply defined rim by a heat treatment under a condition which causes a reflow in the first insulating layer.

Claim 4

A method as claimed in claim 2 in which said first insulating layer comprises a phospho-silicate glass and said heat treatment is carried out at a temperature of about 950° C.-1050° C.

Claim 5

A method as claimed in claim 1 in which said step of forming the first opening comprises an isotropic etching process of the first insulating layer.

Claim 6

A method as claimed in claim 4 in which said isotropic etching is a wet etching process using a hydrofluoric solution as an etching agent.

Claim 7

A method as claimed in claim 1 further comprising a step of patterning the second insulating layer after the step of patterning the wiring electrode such that the second insulating layer is removed from a part of the first insulating layer not covered by the first wiring electrode part.

Claim 8

A method as claimed in claim 1 further comprising a step of patterning the second insulating layer after the step of depositing the second insulating layer such that the second insulating layer is removed from the first insulating layer except for the part covering the first doped region.

Claim 9

A method as claimed in claim 1 further comprising a step of depositing a protective layer on said second insulating layer before the step of depositing the wiring electrode layer.

Claim 10

A method as claimed in claim 8 in which said protective layer comprises polysilicon.

Claim 11

A breakdown-of-insulator-for-conduction type memory cell device comprising: a substrate doped to a first conductive type; a channel region defined in the substrate; first and second doped regions both doped to a second conductive type and defined in the substrate at both sides of said channel region; a gate insulator layer provided on said substrate so as to cover the channel region; a gate electrode deposited on said gate insulator layer; a first insulating layer covering the first doped region, the second doped region, and the gate electrode; a first penetrating opening provided on said first insulating layer in correspondence to the first doped region such that the first doped region is exposed through said first penetrating opening, said first penetrating opening being defined by an inclined first side wall which defines a diameter of said first opening such that the diameter increases towards a top surface of the first insulating layer; a second penetrating opening provided on said first insulating layer in correspondence to the second doped region such that the second doped region is exposed through said second penetrating opening, said second penetrating opening being defined by a second side wall having a straight vertical cross section when taken perpendicularly to the surface of the substrate; a third penetrating opening provided on said first insulating layer in correspondence to the gate electrode such that the gate electrode is exposed through said third penetrating opening, said third penetrating opening being defined by a third side wall having a straight vertical cross section when taken perpendicularly to the surface of the substrate, said second and third penetrating openings further defined by sharp-edge rims to thereby reduce the overall size of said memory cell device; a second insulating layer provided on said first insulating layer in correspondence to said first doped region so as to cover the first doped region exposed through said first penetrating opening, said second insulating layer making a direct contact with the inclined side wall and further making a direct contact with the first doped region; a first wiring electrode deposited on said second insulating layer in correspondence to said first penetrating opening such that the second insulating layer is sandwiched between the first wiring electrode and the first doped region; a second wiring electrode deposited on said second insulating layer in correspondence to said second penetrating opening such that the second wiring electrode makes a contact with said second doped region through said second penetrating hole; and a third wiring electrode deposited on said second insulating layer in correspondence to said third penetrating opening such that the third wiring electrode makes a contact with said gate electrode through said third penetrating opening.

Claim 12

A breakdown-of-insulator-for-conduction type memory cell device comprising: a substrate doped to a first conductive type; a channel region defined in the substrate; first and second doped regions both doped to a second conductive type and defined in the substrate at both sides of said channel region; a gate insulator layer provided on said substrate so as to cover the channel region; a gate electrode deposited on said gate insulator layer; a first insulating layer covering the first doped region, the second doped region, and the gate electrode; a first penetrating opening provided on said first insulating layer in correspondence to the first doped region such that the first doped region is exposed through said first penetrating opening, said first penetrating opening being defined by an inclined first side wall which defines a diameter of said first opening such that the diameter increases towards a top surface of the first insulating layer; a second penetrating opening provided on said first insulating layer in correspondence to the second doped region such that the second doped region is exposed through said second penetrating opening, said second penetrating opening being defined by a second side wall having a straight vertical cross section when taken perpendicularly to the surface of the substrate; a third penetrating opening provided on said first insulating layer in correspondence to the gate electrode such that the gate electrode is exposed through said third penetrating opening, said third penetrating opening being defined by a third side wall having a straight vertical cross section when taken perpendicularly to the surface of the substrate, said second and third penetrating openings further defined by sharp-edge rims to thereby reduce the overall size of said memory cell device; a second insulating layer provided on said first insulating layer in correspondence to said first doped region so as to cover the first doped region exposed through said first penetrating opening, said second insulating layer making a direct contact with the inclined side wall and further making a direct contact with the first doped region; a first wiring electrode deposited on said second insulating layer in correspondence to said first penetrating opening such that the second insulating layer is sandwiched between the first wiring electrode and the first doped region; a second wiring electrode deposited on said second insulating layer in correspondence to said second penetrating opening such that the second wiring electrode makes a contact with said second doped region through said second penetrating hole; and a third wiring electrode deposited on said second insulating layer in correspondence to said third penetrating opening such that the third wiring electrode makes a contact with said gate electrode through said third penetrating opening.