US5077496A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic tracking interface circuit
Assignee: Nortel Networks Ltd
•
Filing: 1990-05-11
•
Granted: 1991-12-31
•
Expires: 2010-05-11
Abstract
Abstract A logic tracking interface circuit includes a signal comparator, a feedback comparator and a logic gate of the type to be driven by the interface circuit. The mean of the inverting and noninverting outputs of the signal comparator is applied as an input to the feedback comparator, the other input being provided by the logic gate. The inverted output of the feedback comparator is used to control the common mode of the signal comparator.
Inventors
- 👤 John A. Wolczanski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:02
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535; H03K19/018542; H03K19/003; H03K19/00369
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
132 words
A logic tracking interface circuit comprising: a signal comparator means having first and second signal inputs, a control input, and first and second outputs; a potential divider, connected between the first and second outputs of the signal comparator means, for providing a means signal value; and a feedback comparator means, having first and second inputs and an output, the first input of the feedback comparator means being connected to the potential divider for receiving the means signal value from said signal comparator means and the output of the feedback comparator means being connected to the control input of said signal comparator means; wherein the second input of the feedback comparator means is connected to a sample logic gate of a type being driven by said interface circuit for providing a decision level.
Claim 2
Dependent Claim
132 words
A logic tracking interface circuit comprising: a signal comparator means having first and second signal inputs, a control input, and first and second outputs; a potential divider, connected between the first and second outputs of the signal comparator means, for providing a means signal value; and a feedback comparator means, having first and second inputs and an output, the first input of the feedback comparator means being connected to the potential divider for receiving the means signal value from said signal comparator means and the output of the feedback comparator means being connected to the control input of said signal comparator means; wherein the second input of the feedback comparator means is connected to a sample logic gate of a type being driven by said interface circuit for providing a decision level.
Claim 3
Dependent Claim
17 words
A circuit as claimed in claim 1 wherein the logic gate means includes an inverting logic gate.
Claim 4
Dependent Claim
22 words
A circuit as claimed in claim 2 wherein the inverting logic gate has a feedback resistor connected between its input and output.
Claim 5
Dependent Claim
20 words
A circuit as claimed in claim 3 wherein the input of the inverting logic gate is capacitively coupled to ground.
Claim 6
Dependent Claim
28 words
A circuit as claimed in claim 3 wherein the input of the inverting logic gate is capacitively coupled via a forward biased diode to the feedback comparator means.
Claim 7
Dependent Claim
17 words
A circuit as claimed in claim 3 wherein the signal comparator means includes output level shifting means.
Claim 8
Dependent Claim
21 words
A circuit as claimed in claim 6 wherein the first input of the feedback comparator means is capacitively coupled to ground.
Claim 9
Dependent Claim
20 words
A circuit as claimed in claim 2 wherein the signal comparator means includes depletion mode metal silicon field effect transistors.
Claim 10
Dependent Claim
20 words
A circuit as claimed in claim 6 wherein the feedback comparator means includes depletion mode metal silicon field effect transistors.
Claim 11
Dependent Claim
21 words
A circuit as claimed in claim 6 wherein the inverting logic gate means includes depletion mode metal silicon field effect transistors.
Claim 12
Dependent Claim
17 words
A circuit as claimed in claim 2 wherein the signal comparator means includes depletion mode GaAs MESFETs.
Claim 13
Dependent Claim
17 words
A circuit as claimed in claim 6 wherein the feedback comparator means includes depletion mode GaAs MESFETs.
Claim 14
Dependent Claim
18 words
A circuit as claimed in claim 6 wherein the inverting logic gate means includes depletion mode GaAs MESFETs.
References Cited (Backward Citations)
US4419595A
Cited
US4612463A
Cited
US4638255A
Cited
US4763021A
Cited
US4890014A
Cited
US4791318A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-30 | 1995-07-01 | 1995-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-30 | 1999-07-01 | 1999-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-30 | 2003-07-01 | 2003-12-31 | $7700.00 | Window Closed / Lapsed |