Computer bus interconnection device

Claim 2

An interface apparatus for interconnecting an AT computer having an AT bus with a VMEbus having a VMEbus backplane to allow the AT computer to respond to VMEbus slave requests as a VMEbus slave, comprising: a circuit card having an AT bus disposed thereon for plugging directly into said VMEbus backplane and for receiving operating power from said VMEbus backplane; a central processing unit (CPU) disposed on said circuit card and connected to said AT bus and forming a portion of said AT computer; a direct memory access (DMA) means connected to said AT bus and forming a portion of said AT computer; interconnection means coupled to said AT bus and to said VMEbus, said interconnection means including bus arbiter means coupled to said DMA means and to said CPU for responding to slave requests from said VMEbus and for receiving and responding to DMA requests from said AT bus; dual access random access memory (RAM) means coupled to said AT bus and to said VMEbus having means whereby both said AT bus and said VMEbus can access said RAM; controller means coupled to said bus arbiter means, to said CPU and to said AT and VMEbuses and being responsive to said bus arbiter and to said CPU for controlling the communication between said RAM means and said AT and VMEbuses; said bus arbiter, upon receipt of a slave request, causing said CPU to be placed in a hold state and inhibiting access to said AT bus by said DMA means and further issusing a slave grant signal to said controller means; said controller means, upon receipt of said slave grant signal and in response to a request by said CPU to access said RAM, causing said RAM to place data on said VMEbus and thereafter causing a data transfer acknowledge (DTACK) signal to be issued to said VMEbus thereby indicating that said AT computer has responded to said slave request.

Claim 3

The interface apparatus of claim 1 wherein said VMEbus provides a backplane and wherein said interface apparatus is adapted to plug directly into said backplane.

Claim 4

The interface apparatus of claim 1 wherein said VMEbus provides a backplane and wherein said interface apparatus further comprises a circuit card adapted to plug directly into said backplane; said circuit card supporting said central processing unit and said dual access random access memory.

Claim 5

The interface apparatus of claim 11 further comprising an input/output circuit disposed on a circuit board adapted to plug directly into said circuit card.

Claim 6

The interface apparatus of claim 4 wherein said input/output circuit comprises disk drive supporting circuitry.

Claim 7

The interface apparatus of claim 4 wherein said input/output circuit comprises monitor supporting circuitry.

Claim 8

The interface apparatus of claim 4 wherein said circuit board and circuit card are provided with plug and jack means for connecting said board and card together in a spatially parallel configuration.

Claim 9

An interface apparatus for interconnecting an AT computer having an AT bus with a VMEbus having a VMEbus backplane to allow the AT computer to respond as a VMEbus master, comprising: a circuit card having an AT bus disposed thereon for plugging directly into said VMEbus backplane and for receiving operating power from said VMEbus backplane; a central processing unit (CPU) connected to said AT bus and forming a portion of said AT computer; interconnection means coupled to said AT bus and to said VMEbus, said interconnection means including master address decoder means coupled to said CPU for decoding predefined addresses; said interconnection means further including requester and controller means coupled to said master address decoder means, to said CPU and to said VMEbus for asserting a VMEbus request to said VMEbus in response to the addressing of said predefined addresses by said CPU and for monitoring said VMEbus and issuing bus ready signals to said CPU following said VMEbus request; said CPU having at least two modes of operation, a real mode and a protected mode, and wherein said interface apparatus further comprising dual access random access memory (RAM) means coupled to said AT bus and to said VMEbus and has means whereby both said AT bus and said VMEbus can access said RAM means and wherein said RAM means is divided into two portions by a real mode/protected mode boundary; wherein said RAM means defines a window between predetermined address limits below the real mode/protected mode boundary and wherein said interconnection means maps addresses between said address limits onto said VMEbus when said CPU is in said real mode; and wherein said RAM means defines predetermined addresses above the real mode/protected mode boundary accessible in said protected mode and wherein said interconnection means maps said predetermined addresses onto said VMEbus when said CPU is in said protected mode.

Claim 10

An interface apparatus for interconnecting an AT computer having an AT bus with a VMEbus having a VMEbus backplane to allow the AT computer to respond as a VMEbus master, comprising: a circuit card having an AT bus disposed thereon for plugging directly into said VMEbus backplane and for receiving operating power from said VMEbus backplane; a central processing unit (CPU) connected to said AT bus and forming a portion of said AT computer; interconnection means coupled to said AT bus and to said VMEbus, said interconnection means including master address decoder means coupled to said CPU for decoding predefined addresses; said interconnection means further including requester and controller means coupled to said master address decoder means, to said CPU and to said VMEbus for asserting a VMEbus request to said VMEbus in response to the addressing of said predefined addresses by said CPU and for monitoring said VMEbus and issuing bus ready signals to said CPU following said VMEbus request; said CPU having at least two modes of operation, a real mode and a protected mode, and wherein said interface apparatus further comprising dual access random access memory (RAM) means coupled to said AT bus and to said VMEbus and has means whereby both said AT bus and said VMEbus can access said RAM means and wherein said RAM means is divided into two portions by a real mode/protected mode boundary; wherein said RAM means defines a window between predetermined address limits below the real mode/protected mode boundary and wherein said interconnection means maps addresses between said address limits onto said VMEbus when said CPU is in said real mode; and wherein said RAM means defines predetermined addresses above the real mode/protected mode boundary accessible in said protected mode and wherein said interconnection means maps said predetermined addresses onto said VMEbus when said CPU is in said protected mode.

Claim 11

The interface apparatus of claim 2 wherein said circuit card supporting said dual access random access memory.

Claim 12

The interface apparatus of claim 9 further comprising an input/output circuit disposed on a circuit board adapted to plug directly into said circuit card.

Claim 13

The interface apparatus of claim 10 wherein said input/output circuit comprises disk drive supporting circuitry.

Claim 14

The interface apparatus of claim 10 wherein said input/output circuit comprises monitor supporting circuitry.

Claim 15

The interface apparatus of claim 10 wherein said circuit board and circuit card are provided with plug and jack means for connecting said board and card together in a spatially parallel configuration.