US5083261A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamically alterable interrupt priority circuit
Assignee: NXP USA Inc
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Filing: 1983-11-03
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Granted: 1992-01-21
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Expires: 2003-11-03
Abstract
Abstract An interrupt priority circuit is used with a data processor which is responsive to interrupt signals from each of a plurality of resources of predetermined priority. A priority encoder receives all of the interrupt signals, and provides an interrupt vector corresponding to the interrupt signal received from the resource having the highest predetermined priority. However, the interrupt priority of a selected resource may be dynamically altered to the highest priority by storing a corresponding priority vector into a priority register. A first multiplexor controlled by the priority vector provides an enable signal whenever an interrupt signal is received from the selected resource. A second multiplexor controlled by the enable signal provides the priority vector if the enable signal is present or the interrupt vector otherwise. A gate controlled by the data processor may be provided to selectively couple the vector provided by the second multiplexor onto the address bus.
Inventors
- 👤 Brian F. Wilkie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:31
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
169 words
In an interrupt priority circuit comprising first means for receiving a plurality of interrupt signals, second means coupled to said first means for selecting one of said interrupt signals according to a predetermined priority scheme and third means coupled to said second means for producing an output signal indicating said selected one of said interrupt signals, the improvement comprising: fourth means for receiving and storing an input signal which designates a highest priority one of said plurality of interrupt signals; first register means for storing said input signal; fifth means coupled to said first register means and responsive to said plurality of interrupt signals for providing an enable signal to said third means if said highest priority interrupt signal signal is received; and wherein said third means is coupled to said fifth means to provide that said output of said third means indicates said highest priority interrupt signal if said means provides said enable signal and indicates said one of said interrupt signals selected by said second means otherwise.
Claim 2
Dependent Claim
169 words
In an interrupt priority circuit comprising first means for receiving a plurality of interrupt signals, second means coupled to said first means for selecting one of said interrupt signals according to a predetermined priority scheme and third means coupled to said second means for producing an output signal indicating said selected one of said interrupt signals, the improvement comprising: fourth means for receiving and storing an input signal which designates a highest priority one of said plurality of interrupt signals; first register means for storing said input signal; fifth means coupled to said first register means and responsive to said plurality of interrupt signals for providing an enable signal to said third means if said highest priority interrupt signal signal is received; and wherein said third means is coupled to said fifth means to provide that said output of said third means indicates said highest priority interrupt signal if said means provides said enable signal and indicates said one of said interrupt signals selected by said second means otherwise.
Claim 3
Independent Claim
72 words
A method of selecting one of a plurality of interrupt signals comprising the steps of: applying a predetermined priority scheme to select one of said plurality of interrupts; receiving an input indicating a highest priority one of said plurality of interrupts; determining whether said highest priority interrupt is active; and overriding said predetermined priority scheme to select said highest priority interrupt only if said highest priority interrupt is determined to be active.
Claim 4
Independent Claim
72 words
A method of selecting one of a plurality of interrupt signals comprising the steps of: applying a predetermined priority scheme to select one of said plurality of interrupts; receiving an input indicating a highest priority one of said plurality of interrupts; determining whether said highest priority interrupt is active; and overriding said predetermined priority scheme to select said highest priority interrupt only if said highest priority interrupt is determined to be active.
Claim 5
Dependent Claim
185 words
A microcomputer comprising: a processor capable of servicing a plurality of interrupt sources; an interrupt priority encoder having inputs coupled to receive interrupt request signals from each of said plurality of interrupt sources and an output; a register having an input coupled to receive a data value from the processor and an output; and first logic means having inputs coupled to receive the interrupt request signals from each of said plurality of interrupt sources and the output of the register for generating an output signal if an interrupt source identified by the data value in the register is currently generating an interrupt request signal; and second logic means having inputs coupled to the output of the first logic means, the output of the interrupt priority encoder and the output of the register and having an output coupled to the processor for providing to the processor a data value corresponding to the data value in the register if the first logic means is generating the output signal and for providing to the processor a data value corresponding to the output of the interrupt priority encoder otherwise.
Claim 6
Dependent Claim
185 words
A microcomputer comprising: a processor capable of servicing a plurality of interrupt sources; an interrupt priority encoder having inputs coupled to receive interrupt request signals from each of said plurality of interrupt sources and an output; a register having an input coupled to receive a data value from the processor and an output; and first logic means having inputs coupled to receive the interrupt request signals from each of said plurality of interrupt sources and the output of the register for generating an output signal if an interrupt source identified by the data value in the register is currently generating an interrupt request signal; and second logic means having inputs coupled to the output of the first logic means, the output of the interrupt priority encoder and the output of the register and having an output coupled to the processor for providing to the processor a data value corresponding to the data value in the register if the first logic means is generating the output signal and for providing to the processor a data value corresponding to the output of the interrupt priority encoder otherwise.
Claim 7
Dependent Claim
14 words
A microcomputer according to claim 3 wherein said second logic means is a multiplexor.
Claim 8
Dependent Claim
18 words
A microcomputer according to claim 4 wherein the data value stored in the register represents an interrupt vector.
Claim 9
Dependent Claim
17 words
A microcomputer according to claim 5 wherein the output of the priority encoder represents an interrupt vector.
Claim 10
Dependent Claim
23 words
A microcomputer according to claim 6 wherein the output of the second logic means is coupled to an address bus of the processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-20 | 1995-07-22 | 1996-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-20 | 1999-07-22 | 2000-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-20 | 2003-07-22 | 2004-01-21 | $7700.00 | Window Closed / Lapsed |