Non-volatile memory structure

Claim 2

A non-volatile semiconductor memory system comprising: a volatile memory circuit for storing binary information in static form; voltage level shifter means for elevating the logic level of the stored binary information, the voltage level shifter means being connected in parallel to the volatile memory circuit; a non-volatile storage means for storing said binary information, the information content of the non-volatile storage means being controlled by the elevated logic levels; and access means for providing access between said non-volatile storage means and said volatile memory circuit, wherein the content of said volatile memory circuit is alterable according to the contents of said non-volatile storage means.

Claim 3

A non-volatile semiconductor memory system according to claim 1, wherein: the non-volatile storage means includes two floating node MOSFET memory cells that are connected in parallel in reverse orientation for storing complimentary information.

Claim 4

A non-volatile semiconductor memory system according to claim 2, wherein: said floating node MOSFET memory cells are single polysilicon layer devices.

Claim 5

A non-volatile semiconductor memory system according to claim 3, wherein: said single polysilicon memory cells include a floating polysilicon node, a tunnel node for supplying a tunnel current to and inducing a potential in said floating node, and a coupling node for inducing a potential on said floating node.

Claim 6

A non-volatile semiconductor memory system comprising: volatile memory circuit for storing binary information in static form; voltage level shifter means for elevating the logic level of the stored binary information, the voltage level shifter means being connected in parallel with the volatile memory circuit; a non-volatile storage means, including two floating node MOSFET memory cells connected in parallel in reverse orientation for storing the binary information in complimentary states, the information content of two floating node MOSFET memory cells being controlled by the elevated logic levels; and access means, including twin mixed parallel coupled pairs of PMOS transistors and NMOS transistors, for providing the access between the non-volatile storage means and the volatile memory circuit so that the contents of the volatile memory circuit is alterable in accordance with the contents of the non-volatile storage means.

Claim 7

A non-volatile semiconductor memory system comprising: volatile memory circuit for storing binary information in static form; voltage level shifter means for elevating the logic level of the stored binary information, the voltage level shifter means being connected in parallel with the volatile memory circuit; a non-volatile storage means, including two floating node MOSFET memory cells connected in parallel in reverse orientation for storing the binary information in complimentary states, the information content of two floating node MOSFET memory cells being controlled by the elevated logic levels; and access means, including twin mixed parallel coupled pairs of PMOS transistors and NMOS transistors, for providing the access between the non-volatile storage means and the volatile memory circuit so that the contents of the volatile memory circuit is alterable in accordance with the contents of the non-volatile storage means.

Claim 8

A non-volatile semiconductor memory system comprising: at least two non-volatile memory cells connected in parallel with opposing orientations, each cell having a node electrode; and two access transistors, one of the NMOS type and one of a PMOS type, the node of each of which is connected to the node electrode of one of the non-volatile memory cells such that each cell is connected to form parallel-connected transistors pairs of mixed transistor types.

Claim 9

A non-volatile semiconductor memory system comprising: at least two non-volatile memory cells connected in parallel with opposing orientations, each cell having a node electrode; and two access transistors, one of the NMOS type and one of a PMOS type, the node of each of which is connected to the node electrode of one of the non-volatile memory cells such that each cell is connected to form parallel-connected transistors pairs of mixed transistor types.

Claim 10

A non-volatile semiconductor memory system comprising: at least two non-volatile memory cells connected in parallel, each cell having a node electrode and each cell having an orientation similar to the other cell; and two access transistors, one of the NMOS type and one of a PMOS type, the node of each of which is connected to the node electrode of one of the nonvolatile memory cells such that each cell is connected to a mixed pair of transistors to form parallel connected transistor pairs of the same transistor type.

Claim 11

A non-volatile semiconductor memory system comprising: at least two non-volatile memory cells connected in parallel, each cell having a node electrode and each cell having an orientation similar to the other cell; and two access transistors, one of the NMOS type and one of a PMOS type, the node of each of which is connected to the node electrode of one of the nonvolatile memory cells such that each cell is connected to a mixed pair of transistors to form parallel connected transistor pairs of the same transistor type.

Claim 12

A non-volatile memory system according to claim 7 further comprising: voltage level shifter means connected in parallel to the non-volatile memory cells for electrically writing information into said cells.

Claim 13

A non-volatile memory system according to claim 6, further comprising: a voltage level shifter means connected in parallel to the non-volatile memory cells for electrically writing information into said cells.