Abstract A clock monitor circuit which is frequency-independent. The crystal terminals on a circuit being monitored for activity may be considered as an inverter combined with a phase delay. The innovative circuit has clock-output and clock-input terminals which are connected to the clock terminals on the circuit being monitored. When a rising edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be high. Similarly, when a falling edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be low. Whenever a low level is detected on a rising edge, or a high level on a falling edge, a counter chain will start counting down. The counter chain will be reset only when a high level is detected on a rising edge AND a low level is detected on the next falling edge. Thus, when the circuit being monitored becomes inactive, the counter chain will start to count down, and will eventually reach zero and generate a watchdog interrupt or reset.
Inventors
👤 Matthew K. Adams
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-09 05:59
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
187 words
An integrated circuit for monitoring clock activity in an associated integrated circuit, comprising: clock-output and clock-input terminals connectable to the crystal terminals on the associated integrated circuit; sampling circuitry, connected to sample the voltage of said clock-input terminal whenever a rising edge appears on said clock-output terminal, and to sample the voltage of said clock-input terminal whenever a falling edge appears on said clock-output terminal; a counter chain, connected to maintain a count value, and to start counting down whenever a low level of said clock-input terminal is detected on a rising edge of said clock-output terminal OR a high level of said clock-input terminal is detected on a falling edge of said clock-out put terminal, and to reset said count value only when a high level of said clock-input terminal is detected on a rising edge of said clock-output terminal AND a low level of said clock-input terminal is detected on the next falling edge of said clock-output terminal, and to provide a zero-crossing output whenever said count value reaches zero; whereby said zero-crossing output provides an indicator that the associated integrated circuit has become inactive.
Claim 2
Dependent Claim
187 words
An integrated circuit for monitoring clock activity in an associated integrated circuit, comprising: clock-output and clock-input terminals connectable to the crystal terminals on the associated integrated circuit; sampling circuitry, connected to sample the voltage of said clock-input terminal whenever a rising edge appears on said clock-output terminal, and to sample the voltage of said clock-input terminal whenever a falling edge appears on said clock-output terminal; a counter chain, connected to maintain a count value, and to start counting down whenever a low level of said clock-input terminal is detected on a rising edge of said clock-output terminal OR a high level of said clock-input terminal is detected on a falling edge of said clock-out put terminal, and to reset said count value only when a high level of said clock-input terminal is detected on a rising edge of said clock-output terminal AND a low level of said clock-input terminal is detected on the next falling edge of said clock-output terminal, and to provide a zero-crossing output whenever said count value reaches zero; whereby said zero-crossing output provides an indicator that the associated integrated circuit has become inactive.