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US5103333A
Expired / Lapsed
US
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Photonic time-slot interchangers using cascade-structured integrated optical switches
Assignee: Verizon Laboratories Inc
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Filing: 1989-10-16
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Granted: 1992-04-07
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Expires: 2009-10-16
Abstract
Abstract A photonic time-slot interchanger with fiber-loop delay-line memories is provided with multistage, cascade-structured integrated optical switches in the write-in, store and circulate and read-out functions to provide improved signal-to-crosstalk ratios and control tolerances, and to increase significantly the number of time slots supported by the improved interchanger.
Inventors
- 👤 Kwang T. Koai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:31
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/0001; H04J; H04J14/00; H04J14/08
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
168 words
An improved photonic time-slot interchanger with fiber-loop delay-lines, comprising: control means to control the operation of said time-slot interchanger and the reconfiguration of time-slots at its output; input means to receive frames of data in preassigned time slots into said time-slot interchanger; memory means comprising a plurality of fiber-loop delay lines; first switching means to switch each time slot of data to a fiber-loop delay-line under the control of said control means; second switching means in each fiber-loop delay-line to control the entry, circulation and exit of data of a time slot for said fiber-loop delay-line; output means to receive said interchanged time slots from said memory means; and third switching means to switch data from said memory means to said output means with the order of said time slots reconfigured under the control of said control means; wherein the improvement comprises: said second switching means is a plurality of interconnected multistage 2×2 cascade-structured integrated optical switches, thereby providing a very high extension ratio for said switching means.
Claim 2
Dependent Claim
168 words
An improved photonic time-slot interchanger with fiber-loop delay-lines, comprising: control means to control the operation of said time-slot interchanger and the reconfiguration of time-slots at its output; input means to receive frames of data in preassigned time slots into said time-slot interchanger; memory means comprising a plurality of fiber-loop delay lines; first switching means to switch each time slot of data to a fiber-loop delay-line under the control of said control means; second switching means in each fiber-loop delay-line to control the entry, circulation and exit of data of a time slot for said fiber-loop delay-line; output means to receive said interchanged time slots from said memory means; and third switching means to switch data from said memory means to said output means with the order of said time slots reconfigured under the control of said control means; wherein the improvement comprises: said second switching means is a plurality of interconnected multistage 2×2 cascade-structured integrated optical switches, thereby providing a very high extension ratio for said switching means.
Claim 3
Dependent Claim
40 words
The improved photonic time-slot interchanger of claim 1, wherein the improvement further comprises: said first switching means is a plurality of N interconnected multistage cascade-structured integrated optical 1×2 switches, thereby providing a 1×N switch with a very high extinction ratio.
Claim 4
Dependent Claim
40 words
The improved photonic time-slot interchanger of claim 1, wherein the improvement further comprises: said third switching means is a plurality of N interconnected multistage cascade-structured integrated optical 2×1 switches thereby providing a N×1 switch with a very high extinction ratio.
Claim 5
Dependent Claim
44 words
The improved photonic time-slot interchanger of claim 1, wherein the improvement further comprises: said first and third switching means are a plurality of N bidirectional interconnected multistage cascade-structured integrated optical 1×2/2×1 switches thereby providing 1×N and N×1 switches with a very high extinction ratio.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-07 | 1995-10-07 | 1996-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-07 | 1999-10-07 | 2000-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-07 | 2003-10-07 | 2004-04-07 | $7700.00 | Window Closed / Lapsed |