Built-in self-test technique for content-addressable memories

Claim 3

The method according to claim 1 wherein the preselected sequences of the write and match/read operations comprise the following seven sequences: (a) (first sequence) performing a write operation W 0 on each successive row of memory cells, the write operation W 0 being performed by writing a word whose bits are all zeros into each successive row of memory cells; (b) (second sequence) performing a match/read operation M 1/0 , a write operation W 1 , the write operation W 0 , and a write operation W 1 in succession on each successive row of memory cells, the match/read operation M 1/0 performed by matching a word whose bits are all ones to the word stored in every row of memory cells while reading the word stored in the successive row of memory cells to ascertain if the word has all zero bits, and each of the write operations W 1 performed by writing a word whose bits are all ones into each successive row of memory cells; (c) (third sequence) successively performing a match/read operation M 0 → and then the write operation W 1 on a single row of memory cells, the match/read operation M 0 → performed by matching each of a sequence of words, obtained by walking a zero through a word of otherwise all one bits, to the word stored in each successive row of memory cells, while successively reading the word stored in each successive row of memory cells to determine if the word stored corresponds to the particular word being matched; (d) (fourth sequence) performing a match/read operation M 1 , the write operation W 0 , a match/read operation M 0 and the write operation W 0 in succession on each row of memory cells, the match/read operation M 1 performed by matching a word whose bits are all ones to the word stored in each successive row of memory cells while reading the word stored in each successive row to ascertain if the stored word has all one bits, and the match/read operation M 0 being performed by matching a word of all zero bits to each successive row of memory cells while reading the word stored in each successive row to ascertain if the stored word has all zero bits; (e) (fifth sequence) performing the match/read operation M 1 , the write operation W 0 , the write operation W 1 , and the write operation W 0 in succession on each successive row of memory cells; (f) (sixth sequence) successively performing a match/read operation M 1 → and then the write operation W 0 on a single row of memory cells, the match/read operation M 1 → performed by matching each of a sequence of words, obtained by walking a one through a word of otherwise all zero bits, to all of the row of memory cells, while successively reading the word stored in the single row of memory cells to determine if the stored word corresponds to the particular word being matched; and (g) (seventh sequence) performing the match/read operation M 0 , the write operation W 1 , the match/read operation M 1 and the write operation W 0 in succession on each row of memory cells.

Claim 4

The method according to claim 2 wherein the rows of memory cells are tested by the steps of: (a) performing the write operation W 0 of the first step sequence of operation successively on each row of memory cells; (b) performing the match/read operation M 1/0 and the write operation W 1 , the write operation W 0 , and the write operation W 1 of the second sequence of operations successively on each row of memory cells; (c) performing the match/read operation M 1 , the write operation W 0 and the match/read operation M 0 on the fourth sequence of operations successively on each row of memory cells; (d) performing the match/read operation M 1 , the write operation W 0 , the write operation W 1 and the write operation W 0 of the fifth sequence of operations successively on each row of memory cells; and (e) performing the match/read operation M 0 , the write operation W 1 , the match/read operation M 1 and the write operation of the seventh sequence of operations successively on each row of cells.

Claim 5

The method according to claim 2 wherein the encoder of the content-addressable memory is tested by executing the write operation W 0 , the match/read operation M 0 and the write operation W 1 of the fourth sequence of operations successively on each row of cells.

Claim 6

The method according to claim 2 wherein the exclusive OR gates of the content-addressable memory are tested by the steps of: (a) performing the write operation W 0 of the first sequence of operations on each row of memory cells and the match/read operation M 1/0 of the second sequence of operations on each successive row of memory cells; (b) performing the write operation W 1 of the second sequence of operations on each row of cells and then performing the match/read operation M 0 → of the third sequence of operations on a single row of memory cells; (c) performing the write operation W 1 of the third sequence of operations on each row of memory cells and then performing the match/read operatioan W 1 of the fourth sequence of operations; and (d) performing the write operation W 0 of the fourth sequence of write operation W 1 , the operations on each row of memory cells and the performing the match/read operation M 1 → of the fifth sequence of operations on the one row of memory cells.

Claim 7

The method according to claim 2 wherein the decoder is tested by the steps of: (a) performing the match/read operation M 1/0 and the last write operation W 1 of the fifth sequence of operations on each successive row of memory cells; and (b) performing the match/read operation M 1 and the last write operation W 0 of the fifth sequence of operations successively on each row of memory cells.

Claim 8

The method according to claim 2 wherein the CAM contains a wild card register for masking bits of a mask word in a mask register and wherein the wild card register is tested by the steps of: (a) applying a word of all ones the match wild card register while simultaneously performing the match/read operation M 1/0 of the second sequence of operations; (b) performing the match/read operation M 1 of the fourth sequence of operations.

Claim 9

A test system for testing a content-addressable memory (CAM) comprised of a plurality of rows of memory cells, each row of memory cells having an address associated therewith and each memory cell in each row having a corresponding, exclusive OR (XOR) gate, a decoder for decoding the address of a row of memory cells into which a data word is to be read or written, a match word register for storing a match word, and an encoder for determining the address of the row containing a word matching the match word, the test system comprising: an up/down counter coupled to the decoder for supplying a count to the decoder of the content addressable memory to address each of a successive row of memory cells; a test pattern generator coupled to the content-addressable memory for supplying the content-addressable memory with a plurality of data words from a group whose bits consist of all ones, all zeros, a walking one in a word of otherwise all zeros and a walking zero in a word of otherwise all ones; first means coupled to the content-addressable memory for compacting data read from the content-addressable memory; second means coupled to the content-addressable memory for compacting data indicative of the address of the rows containing a matching word; and a comparator coupled to the encoder of the content-addressable memory for comparing a match row address output thereby to a predetermined match row address.

Claim 10

A test system for testing a content-addressable memory (CAM) comprised of a plurality of rows of memory cells, each row of memory cells having an address associated therewith and each memory cell in each row having a corresponding, exclusive OR (XOR) gate, a decoder for decoding the address of a row of memory cells into which a data word is to be read or written, a match word register for storing a match word, and an encoder for determining the address of the row containing a word matching the match word, the test system comprising: an up/down counter coupled to the decoder for supplying a count to the decoder of the content addressable memory to address each of a successive row of memory cells; a test pattern generator coupled to the content-addressable memory for supplying the content-addressable memory with a plurality of data words from a group whose bits consist of all ones, all zeros, a walking one in a word of otherwise all zeros and a walking zero in a word of otherwise all ones; first means coupled to the content-addressable memory for compacting data read from the content-addressable memory; second means coupled to the content-addressable memory for compacting data indicative of the address of the rows containing a matching word; and a comparator coupled to the encoder of the content-addressable memory for comparing a match row address output thereby to a predetermined match row address.

Claim 11

The apparatus according to claim 8 wherein the first compactor means comprises: an AND gate coupled to the content-addressable memory for ANDing the contents of the data read from the content-addressable memory; and an OR gate coupled to the content-addressable memory for ORing the contents of the data read from the content-addressable memory.

Claim 12

The apparatus according to claim 8 wherein the second compacting means comprises: an AND gate coupled to the content-addressable memory for ANDing the data indicative of the addresses of the rows containing matching words; and an OR gate coupled to the content-addressable memory for ORing the data indicative of the addresses of the rows containing matching words.

Claim 13

The apparatus according to claim 8 wherein the content-addressable memory further includes a wild card resister for supplying a mask word to mask the match word and wherein the test system includes a wild card generator for supplying a word of all ones and a word of all zeros to test the match word register.