Patent US5111079A successfully refreshed from Google Patents.
US5111079A
Expired / Lapsed
US
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Power reduction circuit for programmable logic device
Assignee: STMicroelectronics lnc USA
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Filing: 1990-06-29
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Granted: 1992-05-05
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Expires: 2010-06-29
Abstract
Abstract According to the present invention, during programming of a programmable logic device, programming information corresponding to an input signal is loaded into a shift register. This input information is compared with programming information corresponding to a second, complementary input signal to determine if the two signals are used by the programmable logic device. If the two inputs are not used, a bit is stored in a memory cell indicating such nonuse. An input buffer is disabled when the bit in the memory cell indicates the complementary signals corresponding to that input buffer are not used.
Inventors
- 👤 Randy C. Steele
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:39
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/0008; H03K19/0016; H03K19/17704; H03K19/1776; H03K19/1778; H03K19/17784
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
128 words
A programmable logic device comprising: a plurality of inputs; a logic array, connected to said inputs, to define a logic function thereof; a storage element connected to each input for storing configuration information for selectively disabling its associated input; a plurality of outputs connected to said array; a programming buffer for holding programming data to program a portion of the device; a plurality of memory elements connected to said programming buffer for storing a copy of data input previously thereto; comparison circuitry connected to said programming buffer and said memory elements for generating a comparison signal indicative of a match between data in said buffer and data in said plurality of memory elements; and means for storing configuration information in said storage elements based upon the comparison signal.
Claim 2
Dependent Claim
128 words
A programmable logic device comprising: a plurality of inputs; a logic array, connected to said inputs, to define a logic function thereof; a storage element connected to each input for storing configuration information for selectively disabling its associated input; a plurality of outputs connected to said array; a programming buffer for holding programming data to program a portion of the device; a plurality of memory elements connected to said programming buffer for storing a copy of data input previously thereto; comparison circuitry connected to said programming buffer and said memory elements for generating a comparison signal indicative of a match between data in said buffer and data in said plurality of memory elements; and means for storing configuration information in said storage elements based upon the comparison signal.
Claim 3
Dependent Claim
23 words
The device of claim 1, wherein each storage element comprises a memory element which can be written to during programming of said device.
Claim 4
Dependent Claim
12 words
The device of claim 2, wherein each storage element comprises an SRAM.
Claim 5
Dependent Claim
15 words
The device of claim 2, wherein each storage element comprises programmable read only storage element.
Claim 6
Dependent Claim
39 words
The device of claim 1, wherein each input is connected to said array through an input buffer, and wherein the associated storage element is set to enable or disable the input buffer based on configuration information in said array.
Claim 7
Dependent Claim
16 words
The programmable logic device of claim 1, wherein said programming buffer comprises a serial shift register.
Claim 8
Dependent Claim
29 words
The programmable logic device of claim 1, wherein said memory elements store a copy of data input for a row which was programmed immediately prior to the current row.
Claim 9
Dependent Claim
76 words
A circuit block for use in programmable logic devices, comprising: a programming buffer for holding programming data to program a portion of the device; a plurality of storage elements connected to said programming buffer for storing a copy of data input previously thereto; and comparison circuitry connected to said programming buffer and said storage elements for generating a signal indicative of a match between data in said buffer and data in said plurality of storage elements.
Claim 10
Dependent Claim
76 words
A circuit block for use in programmable logic devices, comprising: a programming buffer for holding programming data to program a portion of the device; a plurality of storage elements connected to said programming buffer for storing a copy of data input previously thereto; and comparison circuitry connected to said programming buffer and said storage elements for generating a signal indicative of a match between data in said buffer and data in said plurality of storage elements.
Claim 11
Dependent Claim
15 words
The circuit block of claim 8, wherein said programming buffer comprises a serial shift register.
Claim 12
Dependent Claim
27 words
The circuit block of claim 8 wherein each storage element comprises random access memory which can be written to and read from during programming of said device.
Claim 13
Dependent Claim
16 words
The circuit block of claim 8, wherein said comparison circuitry comprises a combination of logic gates.
Claim 14
Dependent Claim
27 words
The circuit of claim 8, wherein said storage elements store a copy of data input for a row which was programmed immediately prior to the current row.
Claim 15
Dependent Claim
116 words
A circuit block for use in programmable logic devices, comprising: a storage cell; an input signal line; and an input buffer connected to said storage cell and said input signal line, wherein said input buffer is disabled if said storage cell has a first value, and is enabled if said storage cell has a second value, and wherein said input buffer comprises a NAND gate connected to said storage cell and said input signal line, a first inverter connected to the output of said NAND gate, and a second inverter connected to the output of said first inverter, wherein the outputs of the first and second inverters define true and complement outputs of said input buffer.
Claim 16
Dependent Claim
116 words
A circuit block for use in programmable logic devices, comprising: a storage cell; an input signal line; and an input buffer connected to said storage cell and said input signal line, wherein said input buffer is disabled if said storage cell has a first value, and is enabled if said storage cell has a second value, and wherein said input buffer comprises a NAND gate connected to said storage cell and said input signal line, a first inverter connected to the output of said NAND gate, and a second inverter connected to the output of said first inverter, wherein the outputs of the first and second inverters define true and complement outputs of said input buffer.
Claim 17
Dependent Claim
98 words
A circuit block for use in programmable logic devices, comprising: a storage cell; an input signal line; and an input buffer connected to said storage cell and said input signal line, wherein said input buffer is disabled if said storage cell has a first value, and is enabled if said storage cell has a second value, and wherein said input buffer allows optional selection of an input signal line or a feedback signal line to be output therefrom, wherein the value in said storage cell enables or disables both the input signal line and the feedback signal line.
Claim 18
Dependent Claim
98 words
A circuit block for use in programmable logic devices, comprising: a storage cell; an input signal line; and an input buffer connected to said storage cell and said input signal line, wherein said input buffer is disabled if said storage cell has a first value, and is enabled if said storage cell has a second value, and wherein said input buffer allows optional selection of an input signal line or a feedback signal line to be output therefrom, wherein the value in said storage cell enables or disables both the input signal line and the feedback signal line.
Claim 19
Independent Claim
81 words
A method for determining whether an input to a programmable logic device will be used in a logic function, comprising the steps of: loading programming data for a row corresponding to the input into a programming buffer; comparing the loaded data to data previously loaded corresponding to a different row which is complementary to the first row; and if the loaded data matches the row which is its complement, then generating a signal indicating that the input will not be used.
Claim 20
Independent Claim
81 words
A method for determining whether an input to a programmable logic device will be used in a logic function, comprising the steps of: loading programming data for a row corresponding to the input into a programming buffer; comparing the loaded data to data previously loaded corresponding to a different row which is complementary to the first row; and if the loaded data matches the row which is its complement, then generating a signal indicating that the input will not be used.
Claim 21
Dependent Claim
29 words
The method of claim 15, wherein said comparing step comprises comparing the loaded data to programming data used to program a row immediately prior to the loaded data row.
Claim 22
Dependent Claim
25 words
The method of claim 15, further comprising the step of: if an input will not be used, disabling an input buffer associated with such input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-05 | 1995-11-04 | 1996-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-05 | 1999-11-04 | 2000-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-05 | 2003-11-04 | 2004-05-05 | $7700.00 | Window Closed / Lapsed |