Abstract A double scanning circuit of improved definition TV (ID-TV) capable for improving resolution of screen and excluding raster by scanning the color signal or the luminance signal of the original signal and the color signal or the luminance signal of the interpolation signal by double speed sequentially. The invention relates to inputting an original signal S1 and an interpolation signal S2 of 8 bits to the line memories through 3-state buffer circuit blocks and 3-state transceiver circuit blocks, and an original signal S1 and an interpolation signal S2 are inputted in said line memories and outputted alternately through a multiplexer, so that double scanning is realized. The present invention provides the effects of doubling the resolution of the screen and also excluding the raster of screen.
A double scanning circuit ID-TV for executing broadcasting signal by digital double speed process, comprising: logic gates; line memories adapted to receive a color signal, said line memories including at least two line memories for receiving said color signal during writing operation by means of a first frequency clock having a frequency, supplied by said logic gates and said line memories; and said line memories other than said at least two line memories being adapted to receive double speed scanning alternatively during reading operation by a frequency clock having a frequency twice that of said first frequency clock.
Claim 2
Dependent Claim
98 words
A double scanning circuit ID-TV for executing broadcasting signal by digital double speed process, comprising: logic gates; line memories adapted to receive a color signal, said line memories including at least two line memories for receiving said color signal during writing operation by means of a first frequency clock having a frequency, supplied by said logic gates and said line memories; and said line memories other than said at least two line memories being adapted to receive double speed scanning alternatively during reading operation by a frequency clock having a frequency twice that of said first frequency clock.
Claim 3
Dependent Claim
39 words
A double scanning circuit of ID-TV according to claim 1 further comprising 3-state tranceiver circuit blocks and wherein data during reading and writing operation of said line memories are organized to be executed through said 3-state tranceiver circuit blocks.
Claim 4
Dependent Claim
48 words
A double scanning circuit of ID-TV according to claim 1 further comprising flipflops having complimentary outputs having a frequency of said first frequency clock, said line memories including terminals wherein reading and writing operations of said line memories are organized by controlling the terminals of said line memories.
Claim 5
Dependent Claim
48 words
A double scanning circuit of ID-TV according to claim 2 further comprising flipflops having complimentary outputs having a frequency of said first frequency clock, said line memories including terminals wherein reading and writing operations of said line memories are organized by controlling the terminals of said line memories.