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US5115412A
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US
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Data read circuit of semiconductor memory device and method of reading data out
Assignee: Mitsubishi Electric Corp
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Filing: 1989-10-23
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Granted: 1992-05-19
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Expires: 2009-10-23
Abstract
Abstract A semiconductor memory device includes a data output bus (I/O, I/O; CD, CD; DB) for transmitting therethrough a read-out potential of a selected one of memory cells (1; MC), and an amplifier circuit (3; 3') for detecting and amplifying a potential on this data output bus. This semiconductor memory device further includes a circuit (Q6, Q7; Q6, Q7, Q12, Q13) for charging the data output bus from a first power supply to a first potential, and a circuit (Q8, Q9, 5; 5', Q8, Q9) for detecting the potential on the data output bus and being activated responsive to shifting of this data output bus potential in the direction of a first supply potential for coupling the data output bus potential to a second power supply to recover the same to the first potential at a high speed. When the data output bus rises in potential above the first potential, the charging circuit does not function, but the recovering circuit functions to recover the potential on this data output bus to the first potential at a high speed by coupling the data input/output bus to a second supply potential. The recovering circuit includes insulated gate type field effect transistors Q8 and Q9 having their gates supplied with a voltage obtained by lowering the first potential further by threshold voltages of these insulated gate type field effect transistors.
Inventors
- 👤 Youichi Tobita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/10; G11C7/1048; G11C7/12
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
146 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of common signal lines each connected to a row of said plurality of memory cells, each said column signal line transmitting thereon data of a selected memory cell; means responsive to an external address for selecting a corresponding column signal line; a data output bus for having a signal transmitted from a selected column signal line; means for sensing and amplifying the signal on said data output bus; first potential setting means provided between a first supply potential and said data output bus for setting said data output bus to a first predetermined potential; and second potential setting means for detecting a potential on said data output bus and for setting said data output bus to said first predetermined potential in response to the detected potential.
Claim 2
Dependent Claim
146 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of common signal lines each connected to a row of said plurality of memory cells, each said column signal line transmitting thereon data of a selected memory cell; means responsive to an external address for selecting a corresponding column signal line; a data output bus for having a signal transmitted from a selected column signal line; means for sensing and amplifying the signal on said data output bus; first potential setting means provided between a first supply potential and said data output bus for setting said data output bus to a first predetermined potential; and second potential setting means for detecting a potential on said data output bus and for setting said data output bus to said first predetermined potential in response to the detected potential.
Claim 3
Dependent Claim
89 words
A semiconductor memory device in accordance with claim 1, wherein: said first potential setting means comprises means for supplying said data output bus with said first predetermined potential being provided as a function of said first supply potential; and said second potential setting means comprises means activated when a detected potential on said data output bus shifts toward said first supply potential from the first predetermined potential, for coupling said data output bus to a second supply potential, thereby resetting said data output bus to said first predetermined potential.
Claim 4
Dependent Claim
83 words
A semiconductor memory device in accordance with claim 1, wherein said second potential setting means comprises first switching element means provided between said data output bus and a second supply potential, and having a threshold voltage for determining conduction/non-conduction thereof, and means for applying to a control terminal of said first switching element means a control voltage having a value shifted in the direction of said second supply potential from said first predetermined potential by an amount substantially equal to said threshold voltage.
Claim 5
Dependent Claim
179 words
A semiconductor memory device in accordance with claim 3, wherein said first potential setting means comprises at least one second switching element means of a first polarity having a threshold voltage and provided between said first supply potential and said data output bus, said second switching element means providing a voltage drop with a value of said threshold voltage thereby setting said data output bus to a potential which is less than said first supply potential by a value equal to the number of said second switching element means multiplied by said threshold voltage; and said control voltage applying means comprises a series connection of third switching element means of said first polarity, fourth switching element means of a second polarity and a resistor between said first supply potential and the control terminal of said first switching element means; and the number of said third switching element means is the same as that of said second switching element means, and the number of said fourth switching element means is the same as that of said first switching element means.
Claim 6
Dependent Claim
28 words
A semiconductor memory device in accordance with claim 4, wherein said first, second, third and fourth switching element means each comprise an insulated gate type field effect transistor.
Claim 7
Dependent Claim
200 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of bit line pairs each connected to a column of said plurality of memory cells and comprising first and second bit lines for transmitting complementary data therethrough; means responsive to an external address for selecting a corresponding bit line pair; a data output bus for having a signal transmitted from a selected pair of the bit lines therethrough, said data output bus having a first data output line for transmitting a signal from said first bit line therethrough and a second data output line for transmitting therethrough a signal from said second bit line; means for sensing and amplifying a potential difference on said data output bus; first potential setting means provided between a first supply potential and each of said first and second data output lines, for setting said first and second data output lines to a first predetermined potential; and second potential setting means for detecting respective potentials on said first and second data output lines and for setting said first and second data output lines to said first predetermined potential in response to the detected respective potentials.
Claim 8
Dependent Claim
200 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of bit line pairs each connected to a column of said plurality of memory cells and comprising first and second bit lines for transmitting complementary data therethrough; means responsive to an external address for selecting a corresponding bit line pair; a data output bus for having a signal transmitted from a selected pair of the bit lines therethrough, said data output bus having a first data output line for transmitting a signal from said first bit line therethrough and a second data output line for transmitting therethrough a signal from said second bit line; means for sensing and amplifying a potential difference on said data output bus; first potential setting means provided between a first supply potential and each of said first and second data output lines, for setting said first and second data output lines to a first predetermined potential; and second potential setting means for detecting respective potentials on said first and second data output lines and for setting said first and second data output lines to said first predetermined potential in response to the detected respective potentials.
Claim 9
Dependent Claim
127 words
A semiconductor memory device in accordance with claim 6, wherein said first potential setting means comprises first means provided between said first supply potential and said first output line for supplying said first data output line with said first predetermined potential, and second means provided between said first supply potential and said second data output line for supplying said second data output line with said first predetermined potential, said first potential being provided as a function of said first supply potential; and said second potential setting means comprises means, activated when detected potential on said first and second data output lines are shifted toward said first supply potential from said first predetermined potential, for resetting said first and second data output lines to said first predetermined potential.
Claim 10
Dependent Claim
113 words
A semiconductor memory device in accordance with claim 6, wherein said second potential setting means comprises first switching element means provided between said first data output line and a second power supply potential, second switching element means provided between said second data output line and said second power supply potential, each of said first and second switching element means having a threshold voltage for determining conduction/non-conduction thereof, and means for applying to a control terminal of each said first and second switching element means a control voltage having a value shifted in the direction of said second supply potential from said first predetermined potential by an amount substantially equal to said threshold voltage.
Claim 11
Dependent Claim
224 words
A semiconductor memory device in accordance with claim 8, wherein said first potential setting means comprises first and second supplying means for supplying said first and second output lines with a first potential, respectively, said first and second supplying means each comprising at least one third switching element means of a first polarity, said third switching element means having a threshold voltage for determining conduction/non-conduction thereof; said third switching element means provided a voltage drop with a value of the threshold voltage thereof, thereby setting said first and second data output lines to a potential which is less than said first supply potential, by a value equal to the number of said third switching element means multiplied by said threshold voltage; said first and second switching element means being of a second polarity; and wherein said control voltage applying means comprises a series connection of fourth switching element means of said first polarity and fifth switching element means of said second polarity, provided between said first supply potential and the control terminal of each said first and second switching element means, the number of said fourth switching element means, and the number of said fifth switching element means being the same as that of said first switching element means, and said first and second supplying means comprising the same number of switching element means.
Claim 12
Dependent Claim
29 words
A semiconductor memory device in accordance with claim 9, wherein said first, second, third, fourth and fifth switching element means each comprises an insulated gate type field effect transistor.
Claim 13
Dependent Claim
213 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of bit lines each connected to a column of said plurality of memory cells; means responsive to an external address for selecting a corresponding bit line; a data output line for transmitting therethrough a signal from a selected one of the bit lines; a reference voltage supply line for transmitting a reference voltage; means for sensing and amplifying a potential difference between said reference voltage supply line and said data output line; first potential setting means provided between a first power supply potential and said data output link for setting said data output line to a first predetermined potential; second potential setting means for detecting a potential on said data output line and for setting said data output line to said first predetermined potential in response to the detected potential; third potential setting means provided between said first power supply potential and said reference voltage supply line for setting said reference voltage supply line to the first predetermined potential; and fourth potential setting means for detecting a potential on said data reference voltage supply line and for setting said reference voltage supply line to said first predetermined potential response to the detected potential.
Claim 14
Dependent Claim
213 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of bit lines each connected to a column of said plurality of memory cells; means responsive to an external address for selecting a corresponding bit line; a data output line for transmitting therethrough a signal from a selected one of the bit lines; a reference voltage supply line for transmitting a reference voltage; means for sensing and amplifying a potential difference between said reference voltage supply line and said data output line; first potential setting means provided between a first power supply potential and said data output link for setting said data output line to a first predetermined potential; second potential setting means for detecting a potential on said data output line and for setting said data output line to said first predetermined potential in response to the detected potential; third potential setting means provided between said first power supply potential and said reference voltage supply line for setting said reference voltage supply line to the first predetermined potential; and fourth potential setting means for detecting a potential on said data reference voltage supply line and for setting said reference voltage supply line to said first predetermined potential response to the detected potential.
Claim 15
Dependent Claim
146 words
A semiconductor memory device in accordance with claim 11, wherein said first potential setting means comprises first supplying means for supplying said data output line with said first predetermined potential, said first predetermined potential being provided as a function of said first power supply potential; said third potential setting means comprises second supplying means for supplying said reference voltage supply signal line with said first predetermined potential; said second potential setting means comprises means, activated when a first detected potential on said data output line is shifted from said first predetermined potential towards said first power supply potential, for resetting said data output line to said first predetermined potential; and said fourth potential setting means comprises means, activated when a second detected potential on said reference voltage supply line is shifted from said first predetermined potential said reference voltage supply line to said first predetermined potential.
Claim 16
Dependent Claim
87 words
A semiconductor memory device in accordance with claim 11, wherein said second potential setting means comprises first switching element means provided between said data output line and a second power supply, said first switching element means having a threshold voltage for determining conduction/non-conduction thereof, and means for applying to a control terminal of said first switching element means a control voltage having a value shifted in the direction of said second supply potential from said first predetermined potential by an amount substantially equal to said threshold voltage.
Claim 17
Dependent Claim
174 words
A semiconductor memory device in accordance with claim 13, wherein said first potential setting means comprises at least one third switching element means of a first polarity having a threshold voltage, said third switching element means providing a voltage drop with a value of said threshold voltage thereby setting said data output line to a potential lower than said first supply potential by a value equal to the number of said third switching element means multiplied by said threshold voltage; said first switching element means is formed of at least one switching transistor of a second polarity; said control voltage applying means comprises a series connection of fourth switching element means of said second polarity, and is arranged between said first power supply potential and the control terminal of said first switching element means; and the number of said fourth switching element means is the same as that of said third switching element means, and the number of said fifth switching element means is the same as that of said first switching element means.
Claim 18
Dependent Claim
29 words
A semiconductor memory device in accordance with claim 14, wherein said first, second, third, fourth and fifth switching element means each comprises an insulated gate type field effect transistor.
Claim 19
Independent Claim
145 words
A method of stabilizing a voltage on a data output line in a semiconductor memory device, said semiconductor memory device having a plurality of memory cells arranged in a matrix of rows and columns, column signal lines each connected to a column of said plurality of memory cells, a data output bus for transmitting therethrough a signal received from a selected one of the column signal lines, means for sensing and amplifying a signal on said data output bus, and circuit means provided between a first supply potential and said data output bus for setting said data output bus to a first predetermined potential, said method comprising the steps of: (a) detecting a potential on said data output bus; and (b) resetting said data output bus to said first predetermined potential in response to a deviation in the detected potential from said first predetermined potential.
Claim 20
Independent Claim
145 words
A method of stabilizing a voltage on a data output line in a semiconductor memory device, said semiconductor memory device having a plurality of memory cells arranged in a matrix of rows and columns, column signal lines each connected to a column of said plurality of memory cells, a data output bus for transmitting therethrough a signal received from a selected one of the column signal lines, means for sensing and amplifying a signal on said data output bus, and circuit means provided between a first supply potential and said data output bus for setting said data output bus to a first predetermined potential, said method comprising the steps of: (a) detecting a potential on said data output bus; and (b) resetting said data output bus to said first predetermined potential in response to a deviation in the detected potential from said first predetermined potential.
Claim 21
Dependent Claim
38 words
A method of claim 16, wherein in step (b) said data output bus is reset to said first predetermined potential in response to a detected potential on said data output bus becoming higher than said first predetermined potential.
Claim 22
Dependent Claim
20 words
A method of claim 17, wherein in step (b) said data output bus is coupled to a second supply potential.
Claim 23
Dependent Claim
59 words
A method of claim 16, wherein in step (b) said data output bus is coupled to a second power supply potential to reset said data output bus to said first predetermined potential in response to a shift of detected potential on said data output bus in the direction of said first power supply potential from said first predetermined potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |