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US5115413A
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Semiconductor memory device
Assignee: Micron Memory Japan Ltd
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Filing: 1990-03-20
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Granted: 1992-05-19
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Expires: 2010-03-20
Abstract
Abstract A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features include a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.
Inventors
- 👤 Katsuyuki Sato
- 👤 Miki Matsumoto
- 👤 Sadayuki Ohkuma
- 👤 Masahiro Ogata
- 👤 Masahiro Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:07
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C7/10; G11C7/1075; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
59 words
A semiconductor memory device comprising: a serial output circuit provided with a serial selector; a serial-use signal line coupled to said serial output circuit; and a data latch circuit coupled between said serial output circuit and said serial-use signal line, wherein said serial output circuit is controlled in accordance with a select signal formed by a Gray code counter.
Claim 2
Dependent Claim
59 words
A semiconductor memory device comprising: a serial output circuit provided with a serial selector; a serial-use signal line coupled to said serial output circuit; and a data latch circuit coupled between said serial output circuit and said serial-use signal line, wherein said serial output circuit is controlled in accordance with a select signal formed by a Gray code counter.
Claim 3
Dependent Claim
69 words
A semiconductor memory device comprising: a plurality of memory mats; and a serial input/output circuit to be shared by said plurality of memory mats, wherein bit lines in the nonselected memory mat which lie between the selected memory mat and-said serial input/output circuit are used as signal transmission paths, and wherein a sense amplifier provided for said nonselected memory mat is operated as an amplifier circuit for signal transmission.
Claim 4
Dependent Claim
69 words
A semiconductor memory device comprising: a plurality of memory mats; and a serial input/output circuit to be shared by said plurality of memory mats, wherein bit lines in the nonselected memory mat which lie between the selected memory mat and-said serial input/output circuit are used as signal transmission paths, and wherein a sense amplifier provided for said nonselected memory mat is operated as an amplifier circuit for signal transmission.
Claim 5
Dependent Claim
143 words
A multi-port semiconductor memory device comprising: a random access memory; a serial access memory coupled to the random access memory; a first input/output port coupled to said random access memory to permit input and output of data to and from said random access memory; a second input/output port coupled to said serial access memory to permit input and output of data to and from said serial access memory; serial input/output lines provided in said serial access memory to couple storage elements in said serial access memory with said second input/output port, wherein said serial input/output lines are each divided into first and second parts to reduce the load of said serial input/output lines; and a first input/output circuit coupled to said first parts of said serial input/output lines and a second input/output circuit coupled to said second parts of said serial input/output lines.
Claim 6
Dependent Claim
143 words
A multi-port semiconductor memory device comprising: a random access memory; a serial access memory coupled to the random access memory; a first input/output port coupled to said random access memory to permit input and output of data to and from said random access memory; a second input/output port coupled to said serial access memory to permit input and output of data to and from said serial access memory; serial input/output lines provided in said serial access memory to couple storage elements in said serial access memory with said second input/output port, wherein said serial input/output lines are each divided into first and second parts to reduce the load of said serial input/output lines; and a first input/output circuit coupled to said first parts of said serial input/output lines and a second input/output circuit coupled to said second parts of said serial input/output lines.
Claim 7
Dependent Claim
27 words
A multi-port semiconductor memory device according to claim 3, wherein said first and second input/output circuits are respectively located at opposite ends of said serial access memory.
Claim 8
Dependent Claim
34 words
A multi-port semiconductor memory device according to claim 3, wherein said first and second input/output circuits are sense amplifiers for respectively amplifying signals on said first and second parts of said serial input/output lines.
Claim 9
Dependent Claim
89 words
A multi-port semiconductor memory device according to claim 3, further comprising: a plurality of random input/output lines provided in said random access memory to couple storage elements in said random access memory with said first input/output port, wherein said random input/output lines are each divided into first and second parts to reduce the load of said random input/output lines; and a third input/output circuit coupled to said first parts of said random input/output lines and a fourth input/output circuit coupled to said second parts of said random input/output lines.
Claim 10
Dependent Claim
34 words
A multi-port semiconductor memory device according to claim 6, wherein said third and fourth input/output circuits are sense amplifiers for respectively amplifying signals on said first and second parts of said random input/output lines.
Claim 11
Dependent Claim
22 words
A multi-port semiconductor memory device according to claim 3, wherein said serial input/output lines are divided at substantially a middle point thereof.
Claim 12
Dependent Claim
25 words
A multi-port semiconductor memory device according to claim 8, wherein said serial input/output lines are divided along a longitudinal direction of said serial access memory.
Claim 13
Dependent Claim
27 words
A multi-port semiconductor memory device according to claim 9, wherein said first and second input/output circuits are respectively located at opposite ends of said serial access memory.
Claim 14
Dependent Claim
25 words
A multi-port semiconductor memory device according to claim 6, wherein said random input/output lines are divided along a longitudinal direction of said random access memory.
Claim 15
Dependent Claim
46 words
A multi-port semiconductor memory device according to claim 6, wherein said first and second input/output lines are respectively located at opposite ends of said serial access memory, and wherein said third and fourth input/output circuits are respectively located at opposite ends of said random access memory.
Claim 16
Dependent Claim
54 words
A multi-port semiconductor memory device according to claim 4, further comprising a first input/output bus coupled to said first input/output circuit to couple said first input/output circuit to said second input/output port, and a second input/output bus coupled to said second input/output circuit to couple said second input/output circuit to said second input/output port.
Claim 17
Dependent Claim
134 words
A multi-port semiconductor memory device according to claim 6, wherein said first and second input/output circuits are respectively located at opposite ends of said serial access memory, and said third and fourth input/output circuits are respectively located at opposite ends of said random access memory, said circuit further comprising: a first input/output bus coupled to said first input/output circuit to couple said first input/output circuit to said second input/output port; a second input/output bus coupled to said second input/output circuit to couple said second input/output circuit to said second input/output port; a third input/output bus coupled to said third input/output circuit to couple said third input/output circuit to said first input/output port; and a fourth input/output bus coupled to said fourth input/output circuit to couple said fourth input/output circuit to said first input/output bus.
Claim 18
Dependent Claim
265 words
A multi-port semiconductor memory device comprising: a random access memory; a serial access memory coupled to said random access memory; a first input/output port coupled to said random access memory to permit input and output of data to and from said random access memory; a second input/output port coupled to said serial access memory to permit input and output of data to and from said serial access memory; serial input/output lines provided in said serial access memory to couple storage elements in said serial access memory to said second input/output port, wherein said serial input/output lines are each divided at substantially a middle point thereof into first and second parts to reduce the load of said serial input/output lines; random input/output lines provided in said random access memory to couple storage elements in said random access memory to said first input/output port, wherein said random input/output lines are each divided substantially at a middle point thereof into first and second parts to reduce the load of said random input/output lines; a first input/output circuit coupled to said first parts of said serial input/output lines and a second input/output circuit coupled to said second parts of said serial input/output lines, wherein said first and second input/output circuits are respectively located at opposite ends of said serial access memory; and a third input/output circuit coupled to said first parts of said random input/output lines and a fourth input/output circuit coupled to said second parts of said random input/output lines, wherein said third and fourth input/output circuits are respectively located at opposite ends of said random access memory.
Claim 19
Dependent Claim
265 words
A multi-port semiconductor memory device comprising: a random access memory; a serial access memory coupled to said random access memory; a first input/output port coupled to said random access memory to permit input and output of data to and from said random access memory; a second input/output port coupled to said serial access memory to permit input and output of data to and from said serial access memory; serial input/output lines provided in said serial access memory to couple storage elements in said serial access memory to said second input/output port, wherein said serial input/output lines are each divided at substantially a middle point thereof into first and second parts to reduce the load of said serial input/output lines; random input/output lines provided in said random access memory to couple storage elements in said random access memory to said first input/output port, wherein said random input/output lines are each divided substantially at a middle point thereof into first and second parts to reduce the load of said random input/output lines; a first input/output circuit coupled to said first parts of said serial input/output lines and a second input/output circuit coupled to said second parts of said serial input/output lines, wherein said first and second input/output circuits are respectively located at opposite ends of said serial access memory; and a third input/output circuit coupled to said first parts of said random input/output lines and a fourth input/output circuit coupled to said second parts of said random input/output lines, wherein said third and fourth input/output circuits are respectively located at opposite ends of said random access memory.
Claim 20
Dependent Claim
60 words
A multi-port semiconductor memory device according to claim 15, wherein said first and second input/output circuits are sense amplifiers for respectively amplifying signals on said first and second parts of said serial input/output lines, and wherein said third and fourth input circuits are sense amplifiers for respectively amplifying signals on said third and fourth parts of said serial input/output lines.
References Cited (Backward Citations)
US3402398A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |