Semiconductor memory device having first and second selecting lines for accessing memory cells

Claim 2

A semiconductor integrated circuit device comprising: data lines which are disposed over a semiconductor substrate as individual sets of complementary data lines, each set including a pair of complementary data lines and each data line of a corresponding pair of complementary data lines being coupled to an identical memory cell; a plurality of memory cells, on said semiconductor substrate, each of which comprises cross-coupled first and second driver MISFETs, first and second switching MISFETs and load elements respectively coupled to said first and second driver MISFETs of said memory cell, said first and second switching MISFETs being coupled between a respective one of said first and second driver MISFETs and a data line of a pair of complementary data lines associated therewith; first selecting lines extending in a row direction over said semiconductor substrate, gate electrodes of said first and second switching MISFETs of said memory cells being integrally formed with said first selecting lines; selecting means, coupled to said first selecting lines, for selecting at least one of said first selecting lines; wirings for supplying a ground potential to said memory cells, said wirings being disposed over said load elements; and second selecting lines coupled to said selecting means and extending in said row direction over said memory cells, wherein said second selecting lines are comprised of a layer which is the same level layer as said wirings, said data lines extending in a column direction over said second selecting lines and said wirings.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said second selecting lines are respectively disposed over predetermined memory cells.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein said wirings extend in said row direction and are disposed over said load elements so as to cover at least a part of said load elements.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein said selecting means selects predetermined first selecting lines at least on the basis of signals of said second selecting lines.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein each of said load elements is comprised of a semiconductor strip, and said semiconductor strip includes first portions and a second portion having a resistivity which is higher than that of said first portions.

Claim 7

A semiconductor integrated circuit device according to claim 5, wherein said second selecting lines are comprised of a first level metal film and said data lines are comprised of a second level metal film.

Claim 8

A semiconductor integrated circuit device according to claim 6, wherein said first selecting lines are comprised of a double-layer film comprising a first film of polycrystalline silicon and a second film of a silicide formed as a compound of silicon and a refractory metal.

Claim 9

A semiconductor integrated circuit device according to claim 7, wherein said first level metal film contains aluminum.

Claim 10

A semiconductor integrated circuit device according to claim 8, wherein said second level metal film contains aluminum.

Claim 11

A semiconductor integrated circuit device according to claim 9, wherein each of said memory cells is a memory cell of a SRAM.

Claim 12

A semiconductor integrated circuit device comprising: data lines which are disposed over a semiconductor substrate as individual sets of complementary data lines, each set including a pair of complementary data lines and each data line of a corresponding pair of complementary data lines being coupled to an identical memory cell; a plurality of memory cells, on said semiconductor substrate, each of which comprises cross-coupled first and second driver MISFETs, first and second switching MISFETs and load element means respectively coupled to said first and second driver MISFETs of said memory cell, said first and second switching MISFETs being coupled between a respective one of said first and second driver MISFETs and a data line of a pair of complementary data lines associated therewith; first selecting lines extending in a row direction over said semiconductor substrate, gate electrodes of said first and second switching MISFETs of said memory cells being integrally formed with said first selecting lines; selecting means, coupled to said first selecting lines, for selecting at least one of said first selecting lines; wiring means, disposed over said load element means, for supplying a ground potential to said memory cells, wherein said wiring means is disposed so as to cover at least a part of said load element means, said wiring means is comprised of a first level metal layer and is extended in said row direction; and second selecting lines coupled to said selecting means and extending in said row direction over said memory cells, wherein said second selecting lines are comprised of a metal layer which is the same level metal layer as said wiring means.

Claim 13

A semiconductor integrated circuit device comprising: data lines which are disposed over a semiconductor substrate as individual sets of complementary data lines, each set including a pair of complementary data lines and each data line of a corresponding pair of complementary data lines being coupled to an identical memory cell; a plurality of memory cells, on said semiconductor substrate, each of which comprises cross-coupled first and second driver MISFETs, first and second switching MISFETs and load element means respectively coupled to said first and second driver MISFETs of said memory cell, said first and second switching MISFETs being coupled between a respective one of said first and second driver MISFETs and a data line of a pair of complementary data lines associated therewith; first selecting lines extending in a row direction over said semiconductor substrate, gate electrodes of said first and second switching MISFETs of said memory cells being integrally formed with said first selecting lines; selecting means, coupled to said first selecting lines, for selecting at least one of said first selecting lines; wiring means, disposed over said load element means, for supplying a ground potential to said memory cells, wherein said wiring means is disposed so as to cover at least a part of said load element means, said wiring means is comprised of a first level metal layer and is extended in said row direction; and second selecting lines coupled to said selecting means and extending in said row direction over said memory cells, wherein said second selecting lines are comprised of a metal layer which is the same level metal layer as said wiring means.

Claim 14

A semiconductor integrated circuit device according to claim 11, wherein said load element means include high resistance portions, and wherein said wiring means is disposed so as to cover at least a part of said high resistance portions.

Claim 15

A semiconductor integrated circuit device according to claim 12, wherein each of said data lines is positioned so as to be substantially aligned over the high resistance portions of said load element means associated therewith.

Claim 16

A semiconductor integrated circuit device according to claim 13, wherein said high resistance portion is comprised of a silicon film having a predetermined resistance value.

Claim 17

A semiconductor integrated circuit device according to claim 14, wherein said second selecting lines are respectively disposed over predetermined memory cells.

Claim 18

A semiconductor integrated circuit device according to claim 15, wherein said silicon film includes first portions and a second portion having a resistivity which is higher than that of said first portions, said second portion is said high resistance portion.

Claim 19

A semiconductor integrated circuit device according to claim 16, wherein said selecting means selects predetermined first selecting lines at least on the basis of signals of said at least one second selecting line.

Claim 20

A semiconductor integrated circuit device according to claim 17, further comprising power source voltage wiring lines, wherein said power source voltage wiring lines are integerally formed with said load element means of said memory cells.

Claim 21

A semiconductor integrated circuit device according to claim 18, wherein said second selecting lines are comprised of a first level metal film and said data lines are comprised of a second level metal film.

Claim 22

A semiconductor integrated circuit device according to claim 19, wherein said first selecting lines are comprised of a double-layer film comprising a first film of polycrystalline silicon and a second film of a silicide formed as a compound of silicon and a refractory metal.

Claim 23

A semiconductor integrated circuit device according to claim 20, wherein said first level metal film contains aluminum.

Claim 24

A semiconductor integrated circuit device according to claim 21, wherein said second level metal film contains aluminum.

Claim 25

A semiconductor integrated circuit device according to claim 22, wherein each of said memory cells is a memory cell of a SRAM.

Claim 26

A semiconductor integrated circuit device according to claim 10, wherein each of said data lines is disposed over corresponding load elements.

Claim 27

A semiconductor integrated circuit device according to claim 24, further comprising power source voltage wiring lines which extend in said row direction, wherein said power source voltage wiring lines are integrally formed with said semiconductor strips of said load elements.