US5126969A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit including non-volatile memory cell capable of temporarily holding information
Assignee: Kawasaki Microelectronics Inc
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Filing: 1990-08-06
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Granted: 1992-06-30
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Expires: 2010-08-06
Abstract
Abstract There are provided, in addition to an ordinary operation word line for controlling a non-volatile memory upon regularly writing or reading information, a testing word line, a selection transistor, and a storage capacitor, whereby an input signal is transferred onto the testing word line upon inspection to switch on the selection transistor and hence the information is transferred into the capacitor through a bit line for writing into and reading from the capacitor. More specifically, the selection transistor and the capacitor are operated as in a DRAM to diagnose the function of an integrated circuit chip without operation of the non-volatile memory.
Inventors
- 👤 Keiichi Kawana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:01
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C29/00; G11C29/04; G11C29/50; G11C14/00; G11C29/08; G11C29/12; G11C29/1201; G11C29/48; G11C7/00; G11C7/24; G11C2029/1202; G11C2029/5002
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
94 words
An integrated circuit including a non-volatile memory cell having a bit line and an output line, the non-volatile memory cell comprising: a non-volatile memory device connected to the output line for permanently storing desired information; a first word line connected to said non-volatile memory device; capacitor means connected to the output line for temporarily storing information; a switching device connected between the output line and the bit line; a second word line connected to said switching device so that said second word line selectively causes the bit line to communicate with the output line.
Claim 2
Dependent Claim
94 words
An integrated circuit including a non-volatile memory cell having a bit line and an output line, the non-volatile memory cell comprising: a non-volatile memory device connected to the output line for permanently storing desired information; a first word line connected to said non-volatile memory device; capacitor means connected to the output line for temporarily storing information; a switching device connected between the output line and the bit line; a second word line connected to said switching device so that said second word line selectively causes the bit line to communicate with the output line.
Claim 3
Dependent Claim
32 words
The integrated circuit of claim 1, wherein said capacitor means for temporarily storing information comprises a resistor connected in series with a capacitor, said resistor supplying voltage to said non-volatile memory device.
Claim 4
Dependent Claim
26 words
The integrated circuit of claim 1, wherein said non-volatile memory device comprises a pair of floating gate transistors, said pair sharing a gate with each other.
Claim 5
Dependent Claim
17 words
The integrated circuit of claim 1, wherein said non-volatile memory device comprises a single floating gate transistor.
Claim 6
Dependent Claim
14 words
The integrated circuit of claim 1, wherein said switching device comprises a selection transistor.
Claim 7
Dependent Claim
41 words
The integrated circuit of claim 1, wherein said second word line selectively causes information on the bit line to be transferred to the output line, a signal containing the information being temporarily stored in said capacitor means for temporarily storing information.
Claim 8
Dependent Claim
39 words
The integrated circuit of claim 6, wherein said first word line renders inoperable an operation of the non-volatile memory device when said second word line selectively causes information on the bit line to be transferred to the output line.
Claim 9
Dependent Claim
19 words
The integrated circuit of claim 1, wherein said capacitor means for temporarily storing information comprises means for noise suppression.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-30 | 1995-12-30 | 1996-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-30 | 1999-12-30 | 2000-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-30 | 2003-12-30 | 2004-06-30 | $7700.00 | Window Closed / Lapsed |