Patent US5129060A successfully refreshed from Google Patents.
US5129060A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed image processing computer
Assignee: BAE Systems National Security Solutions Inc
•
Filing: 1989-01-24
•
Granted: 1992-07-07
•
Expires: 2009-01-24
Abstract
Abstract An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). Mask data is generated by a mask processor coupled to the image algorithm processor (66) for masking one or more pixels in a multi-pixel word and further for masking individual bits within said pixels.
Inventors
- 👤 David M. Pfeiffer
- 👤 David T. Stoner
- 👤 John P. Norsworthy
- 👤 Dwight D. Dipert
- 👤 Jay A. Thompson
- 👤 James A. Fontaine
- 👤 Michael K. Corry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:58
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57; G06F5/00; G06F5/01; G06F5/015; G06F7/544; G06F7/5443; G06T; G06T1/00; G06T1/20; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3828; G06F7/499; G06F7/49905; G06F7/4991; G06F7/49921; G06F7/49942; G06F7/49947
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
70 words
An image processing system, comprising: an image memory for storing pixel data; an address generator for generating addresses for accessing said image memory; a data processor for processing said pixel data associated with said generated addresses; a mask processor associated with said address generator for generating mask data responsive to said generated addresses; and a bus connected between said address generator and said data processor for passing mask information therebetween.
Claim 2
Dependent Claim
70 words
An image processing system, comprising: an image memory for storing pixel data; an address generator for generating addresses for accessing said image memory; a data processor for processing said pixel data associated with said generated addresses; a mask processor associated with said address generator for generating mask data responsive to said generated addresses; and a bus connected between said address generator and said data processor for passing mask information therebetween.
Claim 3
Dependent Claim
21 words
The image processing system of claim 1, further including a plurality of data processors, each coupled together by said mask bus.
Claim 4
Dependent Claim
29 words
The image processing system of claim 2, wherein said mask comprises a multiconductor bus connected to each said data processor so as to achieve a wired arithmetic logic function.
Claim 5
Dependent Claim
24 words
The image processing system of claim 3, wherein each said data processor is connected together by said mask bus by a wired AND function.
Claim 6
Dependent Claim
23 words
The image processing system of claim 3, wherein said address generator is connected to said mask bus to provide a wired arithmetic function.
Claim 7
Dependent Claim
38 words
The image processing system of claim 2, wherein said mask processor comprises a first mask processor and further comprising a second mask processor coupled to said data processor for processing mask data generated by said first mask processor.
Claim 8
Dependent Claim
33 words
The image processing system of claim 6, further including circuitry in each said data processor for receiving mask information from said bus, and for storing said mask information to a register associated therewith.
Claim 9
Dependent Claim
26 words
The image processing system of claim 6 wherein said second mask processor is operable to communicate said generated mask data to others of said data processors.
Claim 10
Dependent Claim
35 words
The image processing system of claim 1, wherein said mask processor includes means for generating a word indicating pixels to be masked and a word indicating which bits in said pixels are to be masked.
Claim 11
Dependent Claim
36 words
The image processing system of claim 9, further including an expander for generating mask information for associating said bit word mask information with each said pixel to be masked as indicated by said pixel mask word.
Claim 12
Dependent Claim
83 words
An image processing system, comprising: an image memory for storing pixel data; circuitry for simultaneously writing plural pixels of data in said memory; an address generator for generating addresses for accessing said image memory; a data processor for processing said pixel data associated with said generated addresses; and a mask processor coupled to said address generator for generating mask data responsive to said generated addresses, said mask data operable to prevent desired pixels from being written into said memory during write operations thereto.
Claim 13
Dependent Claim
83 words
An image processing system, comprising: an image memory for storing pixel data; circuitry for simultaneously writing plural pixels of data in said memory; an address generator for generating addresses for accessing said image memory; a data processor for processing said pixel data associated with said generated addresses; and a mask processor coupled to said address generator for generating mask data responsive to said generated addresses, said mask data operable to prevent desired pixels from being written into said memory during write operations thereto.
Claim 14
Dependent Claim
35 words
The image processing system of claim 11, wherein said mask processor is operable to generate mask data identifying bits within ones of said pixels which should not be written into memory during said write operations.
Claim 15
Independent Claim
63 words
A method of processing image data comprising the steps of: storing the image data in an image memory; generating addresses for accessing the image memory with an address generator; processing the image data associated with the generated addresses with a data processor; generating mask data responsive to the generated addresses; and passing the mask information between the address generator and the data processor.
Claim 16
Independent Claim
63 words
A method of processing image data comprising the steps of: storing the image data in an image memory; generating addresses for accessing the image memory with an address generator; processing the image data associated with the generated addresses with a data processor; generating mask data responsive to the generated addresses; and passing the mask information between the address generator and the data processor.
Claim 17
Dependent Claim
36 words
The method of claim 13 wherein said processing step comprises the step of processing image data associated with the generated addresses using a plurality of data processors, each data processor operable to pass mask information therebetween.
Claim 18
Dependent Claim
23 words
The method of claim 13 and further including the step of storing the mask information in a memory associated with the data processor.
Claim 19
Independent Claim
61 words
The method of processing pixel data comprising the steps of: simultaneously writing plural pixels in said memory; generating addresses for accessing the image memory; processing pixel data associated with the generated addresses; generating mask data responsive to said generated addresses; and preventing pixel data associated with the generated mask data from being written into the image memory during write operations thereto.
Claim 20
Independent Claim
61 words
The method of processing pixel data comprising the steps of: simultaneously writing plural pixels in said memory; generating addresses for accessing the image memory; processing pixel data associated with the generated addresses; generating mask data responsive to said generated addresses; and preventing pixel data associated with the generated mask data from being written into the image memory during write operations thereto.
Claim 21
Dependent Claim
38 words
The method of claim 16 wherein said step of generating mask data comprises the step of generating mask data for identifying bits within ones of the pixels which should not be written into memory during the write operations.
References Cited (Backward Citations)
US3614742A
Cited
US3641555A
Cited
US3614766A
Cited
US3739345A
Cited
US3697678A
Cited
US3735363A
Cited
US3716842A
Cited
US3771141A
Cited
US3787673A
Cited
US3868649A
Cited
US3906480A
Cited
US3996585A
Cited
US3891792A
Cited
US3959774A
Cited
US3938102A
Cited
US3996559A
Cited
US3995253A
Cited
US3976982A
Cited
US4173783A
Cited
US4104624A
Cited
US4070710A
Cited
US4197590B1
Cited
USRE31200F1
Cited
USRE31200E
Cited
US4197590A
Cited
US4057836A
Cited
US4148070A
Cited
US4183058A
Cited
US4128880A
Cited
US4163249A
Cited
US4103331A
Cited
US4120028A
Cited
US4090174A
Cited
US4228430A
Cited
US4121283A
Cited
US4259718A
Cited
US4119955A
Cited
US4414621A
Cited
US4237543A
Cited
US4208723A
Cited
US4165072A
Cited
US4149152A
Cited
US4309691A
Cited
US4266242A
Cited
US4330833A
Cited
US4229797A
Cited
US4303986A
Cited
US4357624A
Cited
US4258385A
Cited
US4498155A
Cited
US4442495A
Cited
US4492956A
Cited
US4491836A
Cited
US4437121A
Cited
US4564915A
Cited
US4475161A
Cited
US4459677A
Cited
US4375638A
Cited
US4395700A
Cited
US4395697A
Cited
US4395698A
Cited
US4484346A
Cited
US4491834B1
Cited
US4491834A
Cited
US4485402A
Cited
US4514818A
Cited
US4386410A
Cited
US4500875A
Cited
US4434502A
Cited
US4472732A
Cited
US4468688A
Cited
US4467412A
Cited
US4439760A
Cited
US4439759A
Cited
US4511962A
Cited
US4463380A
Cited
US4477802A
Cited
US4602286A
Cited
US4482979A
Cited
US4545068A
Cited
US4484349A
Cited
US4563703A
Cited
US4463372A
Cited
US4484187A
Cited
US4435792A
Cited
US4562435A
Cited
US4533910A
Cited
US4543645A
Cited
US4574347A
Cited
US4578812A
Cited
US4511965A
Cited
US4602285A
Cited
US4574277A
Cited
US4571635A
Cited
US4595958A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |