Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: a first external power-supply voltage terminal; a second external power-supply voltage terminal; a reference voltage generator having a first power-supply voltage terminal coupled with said second external power-supply voltage terminal, and having an output signal; an internal power-supply voltage supplier, having a first power-supply voltage terminal coupled with said first external power-supply voltage terminal, for generating an internal power-supply voltage according to the output signal of said reference voltage generator; and an internal circuit having a power-supply voltage terminal supplied with said internal power-supply voltage supplier.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein said internal power-supply voltage supplier has means for conversion of an external power-supply voltage supplied to said second external power-supply voltage terminal into said internal power-supply voltage having a value different from that of the external power-supply voltage.

Claim 4

A semiconductor integrated circuit according to claim 2, further comprising: a third external power-supply voltage terminal coupled with a second power-supply voltage terminal of said reference voltage generator and with a second power-supply voltage terminal of said internal power-supply voltage supplier, wherein said first external power-supply voltage terminal and said second external power-supply voltage terminal are adapted for receiving an external power-supply voltage on the high level side, and wherein said third external power-supply voltage terminal is adapted for receiving an external power-supply voltage on the low level side.

Claim 5

A semiconductor integrated circuit according to claim 3, wherein said means for conversion converts the external power-supply voltage supplied to said second external power-supply voltage terminal into said internal power-supply voltage having a value lower than the external power-supply voltage.

Claim 6

A semiconductor integrated circuit according to claim 2, further comprising: a third external power-supply voltage terminal coupled with a second power-supply voltage terminal of said reference voltage generator and with a second power-supply voltage terminal of said internal power-supply voltage supplier, wherein said first external power-suppy voltage terminal and said second external power-supply voltage terminal are adapted for receiving an external power-supply voltage on the low level side, and wherein said third external power-supply voltage terminal is adapted for receiving an external power-supply voltage on the high level side.

Claim 7

A semiconductor integrated circuit according to claim 5, wherein said means for conversion converts the external power-supply voltage supplied to said second external power-supply voltage terminal into said internal power-supply voltage having a value higher than the external power-supply voltage.

Claim 8

A semiconductor integrated circuit according to claim 4, wherein said semiconductor integrated circuit is formed on a single chip.

Claim 9

A semiconductor integrated circuit according to claim 4, wherein said semiconductor integrated circuit is formed on a p-type substrate.

Claim 10

A semiconductor integrated circuit according to claim 3, wherein said output signal of said reference voltage generator includes a first reference voltage and a second reference voltage, said reference voltage generator including a first resistance-type potential divider coupled to said first power-supply voltage terminal of said reference voltage generator for outputting said first reference voltage, and a second resistance-type potential divider coupled to said second power-supply voltage terminal of said reference voltage generator for outputting said second reference voltage.

Claim 11

A semiconductor integrated circuit according to claim 9, wherein said internal power-supply voltage supplier includes a first MOSFET and a first current mirror circuit and a second MOSFET and a second current mirror circuit, said first current mirror circuit is connected to said first resistance-type potential divider and receives said first reference voltage, said second current mirror circuit is connected to said second resistance-type potential divider and receives said second reference voltage, said first MOSFET being coupled to said first power-supply voltage terminal of said internal power-supply voltage supplier and being driven by said first current mirror circuit, and said second MOSFET being coupled to said second power-supply voltage terminal of said internal power-supply voltage supplier and being driven by said second current mirror circuit.

Claim 12

A semiconductor integrated circuit according to claim 10, wherein said semiconductor integrated circuit is formed with a silicon on sapphire structure.

Claim 13

A semiconductor integrated circuit according to claim 11, wherein said semiconductor integrated circuit is formed with a silicon on insulator structure.

Claim 14

A semiconductor integrated circuit according to claim 4, including an input/output circuit coupled with said internal circuit, and a fourth external power-supply voltage terminal adapted for receiving a power-supply voltage on the high level side, wherein said input/output circuit has a first power-supply voltage terminal coupled with said fourth external power-supply voltage terminal, a second power supply voltage terminal coupled with said third external power-supply voltage terminal, and said input/output circuit being coupled with said internal power-supply voltage from said internal power-supply voltage supplier.

Claim 15

A semiconductor integrated circuit according to claim 13, wherein said input/output circuit includes an output buffer circuit.

Claim 16

A semiconductor integrated circuit according to claim 14, wherein said output buffer circuit includes an output final stage and logic circuits for converting input logic levels of the internal circuit into driving levels for said output final stage, said output final stage includes a p-channel MOSFET and an n-channel MOSFET, and said logic circuits have first and second flip-flop circuits, said first flip-flop circuit including two NAND gates and said second flip-flop circuit including two NOR gates.

Claim 17

A semiconductor integrated circuit according to claim 4, wherein said reference voltage generator includes a resistance-type potential divider for outputting a said output signal.

Claim 18

A semiconductor intergrated circuit according to claim 16, wherein said resistance-type potential divider includes first, second and third p-channel MOSFETs connected in series, each p-channel MOSFET having gate, drain and source electrodes, wherein the gate electrode of each p-channel MOSFET is connected with the source electrode of the same p-channel MOSFET, the source electrode of said first p-channel MOSFET is connected to said first power-supply voltage terminal of said reference voltage generator, and the drain electrode of said third p-channel MOSFET is connected to said second power-supply voltage terminal of said reference voltage generator.

Claim 19

A semiconductor integrated circuit according to claim 16, wherein said reference voltage generator has a relatively small conductance and passes a constant micro-current.

Claim 20

A semiconductor integrated circuit according to claim 17, wherein said reference voltage generator has a relatively small conductance and passes a constant micro-current.

Claim 21

A semiconductor integrated circuit according to claim 4, wherein said internal power-supply voltage supplier includes a first MOSFET and a current mirror circuit, said first MOSFET having a source electrode, a gate electrode and a drain electrode, said source electrode being coupled with said second external power-supply terminal, said gate electrode being coupled with said current mirror circuit, and said drain electrode outputting said internal power-supply voltage.

Claim 22

A semiconductor integrated circuit according to claim 20, wherein said current mirror circuit includes a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET, each MOSFET having source, gate and drain electrodes, wherein said second and third MOSFETs are p-channel MOSFETs, said fourth and fifth MOSFETs are n-channel MOSFETs, and said sixth MOSFET is an n-channel power switch MOSFET, the gate electrode of said fourth MOSFET is supplied with the output signal of said reference voltage generator, the drain electrodes of said fourth MOSFET and said second MOSFET are connected with the gate electrode of said first MOSFET, the source electrodes of said second MOSFET and said third MOSFET are both connected with the source electrode of said first MOSFET, the source electrodes of said fourth MOSFET and said fifth MOSFET are connected with the drain electrode of said sixth MOSFET, the source electrode of said sixth MOSFET is coupled with said third external power-supply voltage terminal the gate electrodes of said second MOSFET and said third MOSFET and the drain electrodes of said third MOSFET and said fifth MOSFET are all commonly connected, and the gate electrode of said fifth MOSFET is connected with drain electrode of said first MOSFET.

Claim 23

A semiconductor integrated circuit according to claim 20, wherein said internal power-supply voltage supplier further includes a capacitor connected to said drain electrode of said first MOSFET.

Claim 24

A semiconductor integrated circuit according to claim 21, wherein said internal power-supply voltage supplier further includes a capacitor connected to said drain electrode of said first MOSFET.

Claim 25

A semiconductor integrated circuit according to claim 23, wherein said capacitor is in the form of an n-channel MOSFET.

Claim 26

A semiconductor integrated circuit according to claim 24, wherein said semiconductor integrated circuit is formed on a p-type substrate.

Claim 27

A semiconductor integrated circuit according to claim 23, wwherein said reference voltage generator includes a resistance-type potential divider for outputting said output signal.

Claim 28

A semiconductor integrated circuit according to claim 26, wherein said reference voltage generator has a relatively small conductance and passes a constant micro-current.

Claim 29

A semiconductor integrated circuit according to claim 26, wherein said resistance-type potential divider includes first, second and third p-channel MOSFETs connected series, each p-channel MOSFET having gate, drain and source electrodes, wherein the gate electrode of each p-channel MOSFET is connected with the source electrode of the same p-channel MOSFET, the source electrode of said first p-channel MOSFET is connected to said first power-supply voltage terminal of said reference voltage generator, and the drain electrode of said third p-channel MOSFET is connected to said second power-supply voltage terminal of said reference voltage generator.

Claim 30

A semiconductor integrated circuit according to claim 28, wherein said reference voltage generator has a relatively small conductance and passes a constant micro-current.

Claim 31

A semiconductor integrated circuit according to claim 28, wherein said semiconductor integrated circuit is formed on a single chip.

Claim 32

A semiconductor integrated ciurcuit according to claim 28, wherein said semiconductor integrated circuit is formed on a p-type substrate.

Claim 33

A semiconductor integrated circuit according to claim 31, wherein n-wells are formed in said p-type substrate, said p-channel MOSFETs being formed in said n-wells, and said n-channel MOSFETs being formed on said p-type substrate.

Claim 34

A microcomputer formed on a semiconductor chip comprising: a first external power-supply voltage terminal; a second external power-supply voltage terminal; reference voltage generator having a first power-supply voltage terminal coupled with said second external power-supply voltage terminal, and having an output signal; an internal power-supply voltage supplier, having a first power-supply voltage terminal coupled with said first external power-supply voltage terminal, for generating an internal power-supply voltage according to the output signal of said reference voltage generator; and an internal circuit having a power-supply voltage terminal supplied with said internal power-supply voltage supplier.

Claim 35

A microcomputer formed on a semiconductor chip comprising: a first external power-supply voltage terminal; a second external power-supply voltage terminal; reference voltage generator having a first power-supply voltage terminal coupled with said second external power-supply voltage terminal, and having an output signal; an internal power-supply voltage supplier, having a first power-supply voltage terminal coupled with said first external power-supply voltage terminal, for generating an internal power-supply voltage according to the output signal of said reference voltage generator; and an internal circuit having a power-supply voltage terminal supplied with said internal power-supply voltage supplier.

Claim 36

A microcomputer according to claim 33, wherein said internal circuit includes a register file, an arithmetic and logic unit, a multiplier, a read-only memory, and a random access memory.

Claim 37

A microcomputer according to claim 34, wherein said microcomputer is formed on a single chip.

Claim 38

A microcomputer according to claim 33, wherein said internal power-supply voltage supplier has means for conversion of an external power-supply voltage supplied to said second external power-supply voltage terminal into said internal power-supply voltage having a value different from that of the external power-supply voltage.

Claim 39

A microcomputer according to claim 36, further comprising: a third external power-supply power-supply voltage terminal coupled with a second power-supply voltage terminal of said reference voltage generator and with a second power-supply voltage terminal of said internal power-supply voltage supplier, wherein said first external power-supply voltage terminal and said second external power-supply voltage terminal are adapted for receiving an external power-supply voltage on the high level side, and wherein said third external power-supply voltage terminal is adapted for receiving an external power-supply voltage on the low level side.

Claim 40

A microcomputer according to claim 37, wherein said means fopr conversion converts the external power-supply voltage supplied to said second external power-supply voltage terminal into said internal power-supply voltage having a value lower than the external power-supply voltage.