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Patent US5132576A successfully refreshed from Google Patents.
US5132576A
Expired / Lapsed
US
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Sense amplifier having load device providing improved access time
Assignee: PLD ACQUISITION CORP
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Filing: 1990-11-05
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Granted: 1992-07-21
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Expires: 2010-11-05
Abstract
Abstract A current sense amplifier for an Erasable Programmable read only memory (EPROM) has an output node with a variable resistance PMOS transistor load device interconnected between a fixed voltage potential and the output node. A gate bias for the PMOS transistor load device is delayed whereby changes in conductance of the load device is delayed in response to a change in voltage on the output node. Access time for the sense amplifier is improved by the delayed change in conductance in the load device.
Inventors
- 👤 Eungjoon Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:46
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
121 words
A load device for a sense amplifier having an output port comprising a variable resistance device comprising a first PMOS transistor having a gate electrode, said variable resistance device connected between said output port and a fixed voltage potential, the conductance of said device increasing as voltage on said output node decreases, and the conductance of said device decreasing as voltage on said output node increases, and means for delaying change in conductance of said device as voltage on said output node changes, said means for delaying change in conductance of said first PMOS transistor comprising a native NMOS transistor interconnected between said output node and said gate electrode, said NMOS transistor having a gate electrode connected to a reference potential.
Claim 2
Dependent Claim
121 words
A load device for a sense amplifier having an output port comprising a variable resistance device comprising a first PMOS transistor having a gate electrode, said variable resistance device connected between said output port and a fixed voltage potential, the conductance of said device increasing as voltage on said output node decreases, and the conductance of said device decreasing as voltage on said output node increases, and means for delaying change in conductance of said device as voltage on said output node changes, said means for delaying change in conductance of said first PMOS transistor comprising a native NMOS transistor interconnected between said output node and said gate electrode, said NMOS transistor having a gate electrode connected to a reference potential.
Claim 3
Dependent Claim
17 words
The load device as defined by claim 1 wherein said reference potential comprises said fixed voltage potential.
Claim 4
Dependent Claim
106 words
A load device for a sense amplifier having an output port comprising a variable resistance device comprising a first PMOS transistor having a gate electrode, said variable resistance device connected between said output port and a fixed voltage potential, the conductance of said device increasing as voltage on said output node decreases, and the conductance of said device decreasing as voltage on said output node increases, and means for delaying change in conductance of said device as voltage on said output node changes, said means for delaying change in conductance of said PMOS transistor comprising a resistor interconnected between said gate electrode and said output node.
Claim 5
Dependent Claim
106 words
A load device for a sense amplifier having an output port comprising a variable resistance device comprising a first PMOS transistor having a gate electrode, said variable resistance device connected between said output port and a fixed voltage potential, the conductance of said device increasing as voltage on said output node decreases, and the conductance of said device decreasing as voltage on said output node increases, and means for delaying change in conductance of said device as voltage on said output node changes, said means for delaying change in conductance of said PMOS transistor comprising a resistor interconnected between said gate electrode and said output node.
Claim 6
Dependent Claim
122 words
A load device for a sense amplifier having an output port comprising a variable resistance device comprising a first PMOS transistor having a gate electrode, said variable resistance device potential, the conductance of said device increasing as voltage on said output node decreases, and the conductance of said device decreasing as voltage on said output node increases, and means for delaying change in conductance of said device as voltage on said output node changes, said means for delaying change in conductance of said PMOS transistor comprising an NMOS transistor having a gate electrode, said NMOS interconnected between said output node and said gate electrode of said first PMOS transistor, and a reference potential connected to said gate electrode of said NMOS transistor.
Claim 7
Dependent Claim
122 words
A load device for a sense amplifier having an output port comprising a variable resistance device comprising a first PMOS transistor having a gate electrode, said variable resistance device potential, the conductance of said device increasing as voltage on said output node decreases, and the conductance of said device decreasing as voltage on said output node increases, and means for delaying change in conductance of said device as voltage on said output node changes, said means for delaying change in conductance of said PMOS transistor comprising an NMOS transistor having a gate electrode, said NMOS interconnected between said output node and said gate electrode of said first PMOS transistor, and a reference potential connected to said gate electrode of said NMOS transistor.
Claim 8
Dependent Claim
135 words
A load device for a sense amplifier having an output port comprising a variable resistance device comprising a first PMOS transistor having a gate electrode, said variable resistance device connected between said output port and a fixed voltage potential, the conductance of said device increasing as voltage on said output node decreases, and the conductance of said device decreasing as voltage on said output node increases, and means for delaying change in conductance of said device as voltage on said output node changes, said means for delaying change in conductance of said first PMOS transistor comprising a second PMOS transistor having a gate electrode, said second PMOS transistor connected between said output node and said gate electrode of said PMOS transistor, and a reference potential connected to said gate electrode of said second PMOS transistor.
Claim 9
Dependent Claim
135 words
A load device for a sense amplifier having an output port comprising a variable resistance device comprising a first PMOS transistor having a gate electrode, said variable resistance device connected between said output port and a fixed voltage potential, the conductance of said device increasing as voltage on said output node decreases, and the conductance of said device decreasing as voltage on said output node increases, and means for delaying change in conductance of said device as voltage on said output node changes, said means for delaying change in conductance of said first PMOS transistor comprising a second PMOS transistor having a gate electrode, said second PMOS transistor connected between said output node and said gate electrode of said PMOS transistor, and a reference potential connected to said gate electrode of said second PMOS transistor.
Claim 10
Dependent Claim
133 words
A current sense amplifier for use with memory in providing a sense current at an output node comprising an input line for receiving data from selected cells in said memory, a variable resistance load device connected between a fixed voltage potential and said output node of said amplifier, said variable resistance device comprising a first PMOS transistor having a gate electrode, means for enabling said sense amplifier by connecting a selected cell to said output node, and means for delaying change in conductance of said variable resistance load device as voltage on said output node changes, said means for delaying change in conductance of said first PMOS transistor comprising a native NMOS transistor interconnected between said output node and gate electrode, said NMOS transistor having a gate electrode connected to a reference potential.
Claim 11
Dependent Claim
133 words
A current sense amplifier for use with memory in providing a sense current at an output node comprising an input line for receiving data from selected cells in said memory, a variable resistance load device connected between a fixed voltage potential and said output node of said amplifier, said variable resistance device comprising a first PMOS transistor having a gate electrode, means for enabling said sense amplifier by connecting a selected cell to said output node, and means for delaying change in conductance of said variable resistance load device as voltage on said output node changes, said means for delaying change in conductance of said first PMOS transistor comprising a native NMOS transistor interconnected between said output node and gate electrode, said NMOS transistor having a gate electrode connected to a reference potential.
Claim 12
Dependent Claim
18 words
The current sense amplifier as defined by claim 6 wherein said reference potential comprises said fixed voltage potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-21 | 1996-01-20 | 1996-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-21 | 2000-01-20 | 2000-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-21 | 2004-01-20 | 2004-07-21 | $7700.00 | Window Closed / Lapsed |