US5132641A
Expired / Lapsed
US
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Apparatus and method for dividing/combining microwave power from an odd number of transistor chips
Assignee: Fujitsu Ltd
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Filing: 1991-05-01
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Granted: 1992-07-21
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Expires: 2011-05-01
Abstract
Abstract A power divider/combiner circuit is disclosed for connecting to a single port, 2N+1 multi-cell monolithic transistor chips, each chip composed of an even number of cells. A planar binary tree type transmission line structure is provided having first and second ends for connecting 2 P trtansmission line ports at the first end to the single port at the second end, where N and P are each integers greater than or equal to 1, and an equal number of cells are connected to each of the 2 P transmission line ports The value of P is chosen such that ##EQU1## where R is an integer greater than 1, and C is the sum total of the number of cells in the 2N+1 chips. R cells are connected to each of the 2 P transmission line ports, and some cells from at least one transistor chip are connected to a transmission line port which is different from the port to which other cells from that one chip are connected.
Inventors
- 👤 Chandra Khandavalli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:41
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/60; H03F3/602; H10; H10W; H10W72/00; H10W72/50; H10W72/541; H10W72/5445; H10W72/551; H10W72/552; H10W72/5522
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
93 words
A power divider/combiner circuit for connecting to a single port 2N+1 multi-cell monolithic transistor chips, each chip composed of an even number of cells, comprising: transmission line means including a planar binary tree type transmission line structure having first and second ends for connecting 2 P transmission line ports at the first end to the single port at the second end, where N and P are each integers greater than or equal to 1; and connecting means for connecting an equal number of cells to each of the 2 P transmission line ports.
Claim 2
Dependent Claim
93 words
A power divider/combiner circuit for connecting to a single port 2N+1 multi-cell monolithic transistor chips, each chip composed of an even number of cells, comprising: transmission line means including a planar binary tree type transmission line structure having first and second ends for connecting 2 P transmission line ports at the first end to the single port at the second end, where N and P are each integers greater than or equal to 1; and connecting means for connecting an equal number of cells to each of the 2 P transmission line ports.
Claim 3
Dependent Claim
50 words
The circuit of claim 1 where P is chosen such that ##EQU6## where R is an integer greater than 1, C is the sum total of the number of cells in the 2N+1 chips, and the connecting means connects R cells to each of the 2 P transmission line ports.
Claim 4
Dependent Claim
37 words
The circuit of claim 2 where some cells from at least one transistor chip are connected to a transmission line port which is different from the port to which other cells from that one chip are connected.
Claim 5
Dependent Claim
15 words
The circuit of claim 1 where the transistor chips are Field Effect transistor (FET) chips.
Claim 6
Dependent Claim
12 words
The circuit of claim 1 where the transistor chips are bipolar chips.
Claim 7
Dependent Claim
17 words
The circuit of claim 1 where each of the 2N+1 chips contains the same number of cells.
Claim 8
Dependent Claim
38 words
The circuit of claim 1 in which signals of a predetermined wavelength are provided thereto, and the width of the transmission line ports at the first end of the transmission line structure are less than half a wavelength.
Claim 9
Dependent Claim
161 words
A power divider/combiner circuit for connecting to single input and output ports 2N+1 multi-cell monolithic transistor chips, each composed of an even number of cells, where each cell includes a signal input and output terminal, comprising: transmission line means including a first planar binary tree type transmission line structure having first and second ends for connecting 2 P transmission line ports at its first end to the single input port at its second end, and a second planar binary tree type transmission line structure having first and second ends for connecting 2 S transmission line ports at its first end to the single output port at its second end, where N, P and S are each integers greater than or equal to 1; and connecting means for connecting an equal number of input terminals to each of the 2 P transmission line ports, and for connecting an equal number of output terminals to each of the 2 S transmission line ports.
Claim 10
Dependent Claim
161 words
A power divider/combiner circuit for connecting to single input and output ports 2N+1 multi-cell monolithic transistor chips, each composed of an even number of cells, where each cell includes a signal input and output terminal, comprising: transmission line means including a first planar binary tree type transmission line structure having first and second ends for connecting 2 P transmission line ports at its first end to the single input port at its second end, and a second planar binary tree type transmission line structure having first and second ends for connecting 2 S transmission line ports at its first end to the single output port at its second end, where N, P and S are each integers greater than or equal to 1; and connecting means for connecting an equal number of input terminals to each of the 2 P transmission line ports, and for connecting an equal number of output terminals to each of the 2 S transmission line ports.
Claim 11
Dependent Claim
83 words
The circuit of claim 8 where P is chosen such that ##EQU7## where R is an integer greater than 1,C is the sum total of the number of cells in the 2N+1 chips, and the connecting means connects R input terminals to each of the 2 P transmission line ports, and where S is chosen such that ##EQU8## where T is an integer greater than 1, and the connecting means connects T output terminals to each of the 2 S transmission line ports.
Claim 12
Dependent Claim
68 words
The circuit of claim 9 where some input terminals from at least one transistor chip are connected to a transmission line port which is different from the port to which other input terminals from that chip are connected, and some output terminals from at least one transistor chip are connected to a transmission line port which is different from the port to which other output terminals are connected.
Claim 13
Dependent Claim
28 words
The circuit of claim 9 where the transistor chips are Field Effect transistor (FET) chips, the input terminals are gate terminals, and the output terminals are drain terminals.
Claim 14
Dependent Claim
25 words
The circuit of claim 9 where the transistor chips are bipolar chips, the input terminals are base terminals, and the output terminals are collector terminals.
Claim 15
Dependent Claim
17 words
The circuit of claim 8 where each of the 2N+1 chips contains the same number of cells.
Claim 16
Dependent Claim
38 words
The circuit of claim 8 in which signals of a predetermined wavelength are provided thereto, and the width of the transmission line ports at the first end of the transmission line structure are less than half a wavelength.
Claim 17
Independent Claim
88 words
A method of connecting to a single port, 2N+1 multi-cell monolithic transistor chips, each chip composed of an even number of cells, comprising the steps of: providing a planar binary tree type transmission line structure having first and second ends for connecting 2 P transmission line ports at the first end to the single port at the second end, where N and P are each integers greater than or equal to 1; and connecting an equal number of cells to each of the 2 P transmission line ports.
Claim 18
Independent Claim
88 words
A method of connecting to a single port, 2N+1 multi-cell monolithic transistor chips, each chip composed of an even number of cells, comprising the steps of: providing a planar binary tree type transmission line structure having first and second ends for connecting 2 P transmission line ports at the first end to the single port at the second end, where N and P are each integers greater than or equal to 1; and connecting an equal number of cells to each of the 2 P transmission line ports.
Claim 19
Dependent Claim
61 words
The method of claim 15 further including the step of selecting P such that ##EQU9## where R is an integer greater than 1, and C is the sum total of the number of cells in the 2N+1 chips; and the step of connecting an equal number of cells includes connecting R cells to each of the 2 P transmission line ports.
Claim 20
Dependent Claim
35 words
The method of claim 16 where the step of connecting an equal number of cells includes connecting cells from at least one transistor chip to more than one of the 2 P transmission line ports.
Claim 21
Dependent Claim
15 words
The method of claim 15 where the transistor chips are Field Effect transistor (FET) chips.
Claim 22
Dependent Claim
12 words
The method of claim 15 where the transistor chips are bipolar chips.
Claim 23
Dependent Claim
17 words
The method of claim 15 where each of the 2N+1 chips contains the same number of cells.
Claim 24
Dependent Claim
41 words
The method of claim 15 further including providing to the transmission line structure signals of a predetermined wavelength, where the width of the transmission line ports at the first end of the transmission line structure are less than half a wavelength.
Claim 25
Independent Claim
153 words
A method for connecting to single input and output ports, 2N+1 multi-cell monolithic transistor chips, each chip composed of an even number of cells, where each cell includes a signal input and output terminal, comprising: providing a first planar binary tree type transmission line structure having first and second ends for connecting 2 P transmission line ports at its first end to the single input port at its second end; providing a second planar binary tree type transmission line structure having first and second ends for connecting 2 S transmission line ports at its first end to the single output port at its second end, where N, P and S are each integers greater than or equal to 1; and connecting an equal number of input terminals to each of the 2 P transmission line ports; and connecting an equal number of output terminals to each of the 2 S transmission line ports.
Claim 26
Independent Claim
153 words
A method for connecting to single input and output ports, 2N+1 multi-cell monolithic transistor chips, each chip composed of an even number of cells, where each cell includes a signal input and output terminal, comprising: providing a first planar binary tree type transmission line structure having first and second ends for connecting 2 P transmission line ports at its first end to the single input port at its second end; providing a second planar binary tree type transmission line structure having first and second ends for connecting 2 S transmission line ports at its first end to the single output port at its second end, where N, P and S are each integers greater than or equal to 1; and connecting an equal number of input terminals to each of the 2 P transmission line ports; and connecting an equal number of output terminals to each of the 2 S transmission line ports.
Claim 27
Dependent Claim
96 words
The method of claim 22 further including the steps of: selecting P such that ##EQU10## where R is an integer greater than 1, and C is the sum total of the number of cells in the 2N+1 chips; selecting S such that ##EQU11## where T is an integer greater than 1; and where the step of connecting the input terminals includes connecting R input terminals to each of the 2 P transmission line ports, and the step of connecting the output terminals includes connecting T output terminals to each of the 2 S transmission line ports.
Claim 28
Dependent Claim
61 words
The method of claim 23 where the step of connecting input terminals includes connecting input terminals from at least one transistor chip to more than one of the 2 P transmission line ports; and the step of connecting output terminals includes connecting output terminals from at least one transistor chip to more than one of the 2 S transmission line ports.
Claim 29
Dependent Claim
28 words
The method of claim 23 where the transistor chips are Field Effect transistor (FET) chips, the input terminals are gate terminals, and the output terminals are drain terminals.
Claim 30
Dependent Claim
25 words
The method of claim 23 where the transistor chips are bipolar chips, the input terminals are base terminals, and the output terminals are collector terminals.
Claim 31
Dependent Claim
17 words
The method of claim 22 where each of the 2N+1 chips contains the same number of cells.
Claim 32
Dependent Claim
41 words
The method of claim 22 further including providing to the transmission line structure signals of a predetermined wavelength, where the width of the transmission line ports at the first end of the transmission line structure are less than half a wavelength.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-21 | 1996-01-20 | 1996-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-21 | 2000-01-20 | 2000-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-21 | 2004-01-20 | 2004-07-21 | $7700.00 | Window Closed / Lapsed |