US5136253A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase comparator having two different phase comparison characteristics
Assignee: Toshiba Corp
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Filing: 1990-09-12
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Granted: 1992-08-04
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Expires: 2010-09-12
Abstract
Abstract A phase comparator has a switching circuit controlled by a switch signal and a phase comparing unit. The switching circuit receives a reference pulse signal having a duty ratio of 50% and a reception data signal having a duty ratio of less than 50%. One of these signals is selected by the switching circuit on the basis of control of the switch signal. The selected signal and an output signal from a voltage-controlled oscillator are supplied to the phase comparing unit. The phase comparing unit compares phases of the two signals. When the phase of the output signal from the voltage-controlled oscillator lags behind the phase of the selected reference pulse signal or reception data signal, the phase comparing unit outputs a first pulse signal, having a width corresponding to a phase difference between the two signals, for advancing the phase of the output signal from the voltage-controlled oscillator. When the phase of the output signal from the voltage-controlled oscillator leads ahead of the phase of the selected reference pulse signal or reception data signal, the phase comparator outputs a second pulse signal, having a width corresponding to a phase difference between the two signals, for delaying the phase of the output signal from the voltage-controlled oscillator.
Inventors
- 👤 Masaji Ueno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:40
CPC Classifications
H; H03; H03L; H03L7/00; H03D; H03D13/00; H03D13/003; H03D13/004; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
268 words
A phase comparator comprising: switching means for receiving a switch signal, and first and second comparison input signals having different duty ratios, and for selecting the first comparison input signal when the switch signal is at a first logic level and the second comparison input signal when the switch signal is at a second logic level; a first D flip-flop circuit having a trigger input terminal for receiving one of the first and second comparison input signals selected by said switching means and a data input terminal for receiving a level "H" signal; a second D flip-flop circuit having a trigger input terminal for receiving an output signal from a voltage-controlled oscillator and a data input terminal for receiving a level "H" signal; pulse signal output means, coupled to said first and second D flip-flop circuits, for outputting a first control signal for advancing a phase of an output signal from said voltage-controlled oscillator and a second control signal for delaying the phase of the output signal from said voltage-controlled oscillator based on output signals from said first and second D flip-flop circuits and the switch signal; first reset means, coupled to said first and second D flip-flop circuits, for outputting a reset signal to said first D flip-flop circuit based on the output signals from said first and second D flip-flop circuits and the switch signal; and second reset means, coupled to said first and second D flip-flop circuits, for outputting a reset signal to said second D flip-flop circuit based on the output signals from said first and second D flip-flop circuits and the switch signal.
Claim 2
Dependent Claim
268 words
A phase comparator comprising: switching means for receiving a switch signal, and first and second comparison input signals having different duty ratios, and for selecting the first comparison input signal when the switch signal is at a first logic level and the second comparison input signal when the switch signal is at a second logic level; a first D flip-flop circuit having a trigger input terminal for receiving one of the first and second comparison input signals selected by said switching means and a data input terminal for receiving a level "H" signal; a second D flip-flop circuit having a trigger input terminal for receiving an output signal from a voltage-controlled oscillator and a data input terminal for receiving a level "H" signal; pulse signal output means, coupled to said first and second D flip-flop circuits, for outputting a first control signal for advancing a phase of an output signal from said voltage-controlled oscillator and a second control signal for delaying the phase of the output signal from said voltage-controlled oscillator based on output signals from said first and second D flip-flop circuits and the switch signal; first reset means, coupled to said first and second D flip-flop circuits, for outputting a reset signal to said first D flip-flop circuit based on the output signals from said first and second D flip-flop circuits and the switch signal; and second reset means, coupled to said first and second D flip-flop circuits, for outputting a reset signal to said second D flip-flop circuit based on the output signals from said first and second D flip-flop circuits and the switch signal.
Claim 3
Dependent Claim
23 words
A comparator according to claim 1, wherein the first comparison input signal is a reference pulse signal having a duty ratio of 50%.
Claim 4
Dependent Claim
25 words
A comparator according to claim 1, wherein the second comparison input signal is a reception data signal having a duty ratio of less than 50%.
Claim 5
Dependent Claim
19 words
A comparator according to claim 1, wherein the comparison reference signal is an output signal from a voltage-controlled oscillator.
Claim 6
Dependent Claim
108 words
A comparator according to claim 1, wherein said pulse signal output means includes first logic means for ORing an inverted output from said first D flip-flop circuit and an inverted output from said second D flip-flop circuit, second logic means for ORing an output from said first logic means and the switch signal, third logic means for ANDing an output from said second logic means and the output from said first D flip-flop circuit and outputting the first control signal, and fourth logic means for ANDing an output from said second logic means and the output from said second D flip-flop circuit and outputting the second control signal.
Claim 7
Dependent Claim
56 words
A comparator according to claim 5, wherein said first D flip-flop circuit is set in response to a rising edge of one of the first and second comparison input signals selected by said switching means, and said second D flip-flop circuit is set in response to a rising edge of the output from said voltage-controlled oscillator.
Claim 8
Dependent Claim
76 words
A comparator according to claim 5, further comprising inverting means for inverting the output signal from said voltage-controlled oscillator in response to the switch signal, wherein said first D flip-flop circuit is set in response to a falling edge of one of the first and second comparison input signals selected by said switch means, and said second D flip-flop circuit is set in response to a falling edge of the output signal from said voltage-controlled oscillator.
Claim 9
Dependent Claim
56 words
A comparator according to claim 5, wherein said first reset means outputs the reset signal when the switch signal is at level "L" and the output from said first logic means is at level "L", and when the switch signal is at level "H" and the output from said first logic means is at level "L".
Claim 10
Dependent Claim
68 words
A comparator according to claim 5, wherein said second reset means outputs the reset signal when the switch signal is at level "L" and the output from said first logic means is at level "L", and when the switch signal is at level "H", the output from said first D flip-flop circuit is at level "L", and the output signal from said voltage-controlled oscillator is at level "L".
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-04 | 1996-02-03 | 1996-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-04 | 2000-02-03 | 2000-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-04 | 2004-02-03 | 2004-08-04 | $7700.00 | Window Closed / Lapsed |