Plural stage voltage booster circuit with efficient electric charge transfer between successive stages

Claim 2

A voltage booster circuit for use in a non-volatile semiconductor memory, said voltage booster circuit comprising: an electric charge supply element having one terminal side for connection to a power source voltage terminal; an electric charge transfer element having one terminal side connected to the other terminal side of said electric charge supply element; a first node disposed in the connection between the other terminal side of said electric charge supply element and the one terminal side of said electric charge transfer element; a first capacitor connected at one end to said first node; the electric potential of said first node rising in response to the application of a first clock signal to the other end of said first capacitor; a second electric charge supply element having one terminal side connected between said first node and said first capacitor; said electric charge transfer element having control means between the one terminal side and the other terminal side thereof; an output terminal connected to the other terminal side of said electric charge transfer element; a second node connected to said control means of said electric charge transfer element; a second capacitor connected at one end to said second node; the other terminal side of said second electric charge supply element being connected to said second node between said control means of said electric charge transfer element and said second capacitor; the electric potential of said second node rising in response to the application of a second clock signal to the other end of said second capacitor; and the increased electric potential of said second node being communicated to said control means of said electric charge transfer element to render said electric charge transfer element conductive for transferring electric potential from said first node to said output terminal at an increased voltage magnitude.

Claim 3

A voltage booster circuit as set forth in claim 1, further including a second electric charge transfer element having one terminal side connected between said first node and said first capacitor and the other terminal side connected between said control means of the first-mentioned said electric charge transfer element and said second capacitor; and said second electric charge transfer element having control means between the one terminal side and the other terminal side thereof and being rendered conductive in response to the increased electric potential of said second node communicated to said control means of said first-mentioned electric charge transfer element and to said control means of said second electric charge transfer element for stabilizing said second node at an electric potential higher than the electric potential of said first node.

Claim 4

A voltage booster circuit as set forth in claim 1, wherein said electric charge supply elements and said electric charge transfer element are MOS transistors having respective source and drain regions and a gate electrode; and said control means of said electric charge transfer element is the gate electrode of the MOS transistor which is the electric charge transfer element.

Claim 5

A voltage booster circuit for use in a non-volatile semiconductor memory, said voltage booster circuit comprising: a plurality of successive stages, each of said plurality of stages comprising: an electric charge supply element having one terminal side for connection to a power source voltage terminal, an electric charge transfer element having one terminal side connected to the other terminal side of said electric charge supply element, a first node disposed in the connection between the other terminal side of said electric charge supply element and the one terminal side of said electric charge transfer element, a first capacitor connected at one end to said first node, the electric potential of said first node rising in response to the application of a first clock signal to the other end of said first capacitor, a second electric charge supply element having one terminal side connected between said first node and said first capacitor, said electric charge transfer element having control means between the one terminal side and the other terminal side thereof, an output terminal connected to the other terminal side of said electric charge transfer element, a second node connected to said control means of said electric charge transfer element, a second capacitor connected at one end to said second node, the other terminal side of said second electric charge supply element being connected to said second node between said control means of said electric charge transfer element and said second capacitor, the electric potential of said second node rising in response to the application of a second clock signal to the other end of said second capacitor, and the increased electric potential of said second node being communicated to said control means of said electric charge transfer element to render said electric charge transfer element conductive for transferring electric potential from said first node to said output terminal at an increased voltage magnitude; wherein said output terminal of a first stage of said plurality of stages is the first node of the next successive stage such that the electric potential of said second nodes of the successive stages included in said plurality of stages is communicated to said control means of said electric charge transfer element of said stage corresponding thereto to render said electric charge transfer element conductive for transferring electric potential from said first node to said output terminal of the corresponding stage at an increased voltage magnitude such that the voltage magnitude is boosted to increased magnitudes as the electric potential is transferred from stage to stage to the output terminal of the last stage included in said plurality of stages.

Claim 6

A voltage booster circuit for use in a non-volatile semiconductor memory, said voltage booster circuit comprising: a plurality of successive stages, each of said plurality of stages comprising: an electric charge supply element having one terminal side for connection to a power source voltage terminal, an electric charge transfer element having one terminal side connected to the other terminal side of said electric charge supply element, a first node disposed in the connection between the other terminal side of said electric charge supply element and the one terminal side of said electric charge transfer element, a first capacitor connected at one end to said first node, the electric potential of said first node rising in response to the application of a first clock signal to the other end of said first capacitor, a second electric charge supply element having one terminal side connected between said first node and said first capacitor, said electric charge transfer element having control means between the one terminal side and the other terminal side thereof, an output terminal connected to the other terminal side of said electric charge transfer element, a second node connected to said control means of said electric charge transfer element, a second capacitor connected at one end to said second node, the other terminal side of said second electric charge supply element being connected to said second node between said control means of said electric charge transfer element and said second capacitor, the electric potential of said second node rising in response to the application of a second clock signal to the other end of said second capacitor, and the increased electric potential of said second node being communicated to said control means of said electric charge transfer element to render said electric charge transfer element conductive for transferring electric potential from said first node to said output terminal at an increased voltage magnitude; wherein said output terminal of a first stage of said plurality of stages is the first node of the next successive stage such that the electric potential of said second nodes of the successive stages included in said plurality of stages is communicated to said control means of said electric charge transfer element of said stage corresponding thereto to render said electric charge transfer element conductive for transferring electric potential from said first node to said output terminal of the corresponding stage at an increased voltage magnitude such that the voltage magnitude is boosted to increased magnitudes as the electric potential is transferred from stage to stage to the output terminal of the last stage included in said plurality of stages.

Claim 7

A voltage booster circuit as set forth in claim 4, wherein each stage of said plurality of stages further includes a second electric charge transfer element having one terminal side connected between said first node and said first capacitor and the other terminal side connected between said control means of the first-mentioned said electric charge transfer element and said second capacitor; and said second electric charge transfer element having control means between the one terminal side and the other terminal side thereof and being rendered conductive in response to the increased electric potential of said second node communicated to said control means of said first-mentioned electric charge transfer element and to said control means of said second electric charge transfer element for stabilizing said second node at an electric potential higher than the electric potential of said first node.

Claim 8

A voltage booster circuit as set forth in claim 4, wherein said electric charge supply elements and said electric charge transfer element included in each stage of said plurality of stages are MOS transistors having respective source and drain regions and a gate electrode; and said control means of said electric charge transfer element is the gate electrode of the MOS transistor which is the electric charge transfer element.

Claim 9

A voltage booster circuit as set forth in claim 4, wherein alternate stages of said plurality of stages are operated from third and fourth clock signals as contrasted to said first and second clock signals; the electric potential of said first node of said alternate stage rising in response to the application of said third clock signal to the other end of capacitor of said alternate stage; and the electric potential of said second node of said alternate stage rising in response to the application of said fourth clock signal to the other end of said second capacitor of said alternate stage.

Claim 10

A voltage booster circuit as set forth in claim 5, wherein alternate stages of said plurality of stages are operated from third and fourth clock signals as contrasted to said first and second clock signals; the electric potential of said first node of said alternate stage rising in response to the application of said third clock signal to the other end of said first capacitor of said alternate stage; and the electric potential of said second node of said alternate stage rising in response to the application of said fourth clock signal to the other end of said second capacitor of said alternate stage.