High speed semiconductor memory having a direct-bypass signal path

Claim 1

A semiconductor integrated circuit device comprising: a plurality of memory cells; a first sense amplifier which amplifies complementary signals read out from a selected one of said plurality of memory cells and provides at complementary outputs thereof complementary output signals; a latch circuit which has complementary signal lines for receiving data of said complementary output signals from said first sense amplifier and stores said data therein; a circuit having complementary inputs coupled to receive the data on said complementary signals of said latch circuit, said circuit including a second sense amplifier and an output buffer, said second sense amplifier having complementary inputs connected to the complementary inputs of said circuit, said output buffer having complementary inputs connected to complementary outputs of said second sense amplifier, and said output buffer outputting an output signal from an output terminal thereof; first pass-gates which are connected between the complementary outputs of said first sense amplifier and the complementary signal lines of said latch circuit; second pass-gates which are connected between the complementary signal lines of said latch circuit and the complementary inputs of said circuit; and signal paths which directly transmit the complementary output signals from said first sense amplifier to the complementary inputs of said circuit and which bypass said first pass-gates, said latch circuit and said second pass-gates, wherein said signal paths effect a direct connection, without any intervening elements, from the complementary outputs of said first sense amplifier to the complementary inputs of said second sense amplifier, and wherein the complementary output signals of said first sense amplifier are at first directly transmitted to the complementary inputs of said circuit through said signal paths, whereby said output buffer generates the output signal in response to the complementary output signals of said first sense amplifier, as transmitted to said circuit from said signal paths, and thereafter said first pass-gates and said second pass-gates are respectively brought into a signal-through condition, and said first sense amplifier is controllably brought to a non-activated condition or to a low gain-low power consumption operating state.