Patent US5155348A successfully refreshed from Google Patents.
US5155348A
Expired / Lapsed
US
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Read-out circuit for a photodetector
Assignee: Qinetiq Ltd
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Filing: 1989-08-31
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Granted: 1992-10-13
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Expires: 2009-08-31
Abstract
Abstract A read-out circuit for a photodetector incorporates a photodiode detector (1) connected via a preamplifier (2) to a storage capacitor (C 5 ). The capacitor (C 5 ) is also connected to a constant current circuit (C c , T 3 to T 7 ) providing a correction current controlled by a voltage on a reference capacitor (C c ). The reference capacitor (C c ) is charged by the amplified photodiode output current during a calibration phase. During a measurement phase, the storage capacitor (C 5 ) integrates the difference between the amplified photodiode output current and the correction current. This provides pedestal signal substraction at the signal integration point. An array of photodetectors may be provided with a corresponding array of read-out circuits integrated in a single semiconductor substrate.
Inventors
- 👤 Ronald A. Ballingal
- 👤 Ian D. Blenkinsop
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:09
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/60; H04N25/63; H04N25/20; H04N25/62; H04N25/626
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
77 words
A read-out circuit for a photodetector (1), the circuit including: correcting means (C c , T 3 to T 7 ) for deriving a correction signal from the photodetector output during a calibration phase; and integrating means (C s , T 1 ) for concurrently receiving a measurement phase signal derived from the photodetector output and said correction signal during a measurement phase, and for integrating any difference between said measurement phase signal and said correction signal.
Claim 2
Dependent Claim
77 words
A read-out circuit for a photodetector (1), the circuit including: correcting means (C c , T 3 to T 7 ) for deriving a correction signal from the photodetector output during a calibration phase; and integrating means (C s , T 1 ) for concurrently receiving a measurement phase signal derived from the photodetector output and said correction signal during a measurement phase, and for integrating any difference between said measurement phase signal and said correction signal.
Claim 3
Dependent Claim
56 words
A read-out circuit according to claim 1 wherein said integrating means includes a storage capacitor (C s ) chargeable to a present voltage, and said photodetector (1) output and said correction signal comprise currents in counterflow during the measurement phase and produce a net current difference signal for integrating by the storage capacitor (C s ).
Claim 4
Dependent Claim
58 words
A read-out circuit according to claim 2 wherein said correcting means (C c , T 3 to T 7 comprises a constant current circuit having an output current controlled by a bias voltage across a reference capacitor (C c ), the reference capacitor (C c ) being chargeable in response to the photodetector output during the calibration phase.
Claim 5
Dependent Claim
88 words
An array of photodetectors, each photodetector having a respective readout circuit, each circuit including: correcting means (C c , T 3 to T 7 ) for deriving a respective correction signal from its associated photodetector output during a calibration phase; and integrating means (C s , T 1 ) for concurrently receiving a measurement phase signal derived from the associated photodetector output and said respective correction signal during a measurement phase, and for integrating any difference between said measurement phase signal and said correction signal for each photodetector.
Claim 6
Dependent Claim
88 words
An array of photodetectors, each photodetector having a respective readout circuit, each circuit including: correcting means (C c , T 3 to T 7 ) for deriving a respective correction signal from its associated photodetector output during a calibration phase; and integrating means (C s , T 1 ) for concurrently receiving a measurement phase signal derived from the associated photodetector output and said respective correction signal during a measurement phase, and for integrating any difference between said measurement phase signal and said correction signal for each photodetector.
Claim 7
Dependent Claim
56 words
An array of photodetectors according to claim 4 wherein each integrating means includes a storage capacitor (C s ) chargeable to a present voltage, and each photodetector output and respective correction signal comprise counterflowing signal currents during measurement phase and produce a net current difference signal for integration by the respective storage capacitor (C s ).
Claim 8
Dependent Claim
22 words
An array of photodetectors according to claim 4 wherein said respective read-out circuits are integrated in a common substrate of semiconductor material.
Claim 9
Dependent Claim
35 words
An array of photodetectors according to claim 4, further including means for exposing the photodetectors to one of a defocussed scene image, a diffused scene image, and a substantially uniform source, during the calibration phase.
Claim 10
Dependent Claim
73 words
In a read-out circuit for a photodetector, the circuit including correcting means arranged to derive a correction signal from the photodetector output during a calibration phase, and integrating means arranged to receive a measurement phase signal derived from the photodetector output during a measurement phase, the improvement comprising the integrating means is arranged to receive the measurement phase signal and the correction signal concurrently during the measurement phase and to integrate their difference.
Claim 11
Dependent Claim
73 words
In a read-out circuit for a photodetector, the circuit including correcting means arranged to derive a correction signal from the photodetector output during a calibration phase, and integrating means arranged to receive a measurement phase signal derived from the photodetector output during a measurement phase, the improvement comprising the integrating means is arranged to receive the measurement phase signal and the correction signal concurrently during the measurement phase and to integrate their difference.
Claim 12
Dependent Claim
55 words
A read-out circuit according to claim 8 wherein the integrating means includes a storage capacitor chargeable to a present voltage, and the photodetector and the correcting means are arranged to give rise to respective signal currents in counterflow during the measurement phase to produce a net current difference signal for integrating by the storage capacitor.
Claim 13
Dependent Claim
44 words
A read-out circuit according to claim 9 wherein the correcting means is a constant current circuit having an output current controlled by a bias voltage across a reference capacitor, the reference capacitor being chargeable in response to the photodetector output during the calibration phase.
Claim 14
Dependent Claim
80 words
In an array of photodetectors each having a respective read-out circuit, each circuit including correcting means arranged to derive a respective correction signal from its associated photodetector output during a calibration phase and integrating means arranged to receive a measurement phase signal derived from the associated photodetector output during a measurement phase, the improvement comprising each integrating means is arranged to receive the respective measurement phase signal and correction signal concurrently during the measurement phase and to integrate their difference.
Claim 15
Dependent Claim
80 words
In an array of photodetectors each having a respective read-out circuit, each circuit including correcting means arranged to derive a respective correction signal from its associated photodetector output during a calibration phase and integrating means arranged to receive a measurement phase signal derived from the associated photodetector output during a measurement phase, the improvement comprising each integrating means is arranged to receive the respective measurement phase signal and correction signal concurrently during the measurement phase and to integrate their difference.
Claim 16
Dependent Claim
59 words
An array of photodetectors according to claim 11 wherein each integrating means includes a storage capacitor chargeable to a preset voltage, and the respective photodetector and correcting means in each circuit are arranged in combination to give rise to counterflowing signal currents during measurement phase to produce a net current difference signal for integration by the respective storage capacitor.
Claim 17
Dependent Claim
21 words
An array of photodetectors according to claim 12 wherein the read-out circuits are integrated in a common substrate of semiconductor material.
Claim 18
Dependent Claim
37 words
An array of photodetectors according to claim 12 including means for exposing the photodetectors in each circuit to any one of a defocussed scene image, a diffused scene image and a substantially uniform source during calibration phase.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |