Drive circuit comprising a subsidiary drive circuit

Claim 2

A driving circuit including an input terminal supplied with an input signal having one of logic one and zero levels and an output terminal for driving a load circuit connected to said output terminal in response to an output signal having one of a predetermine positive voltage and a ground potential said driving circuit comprising: a first inverter connected to said input terminal for inverting said input signal to produce a first inverted signal having logic zero and logic one levels when said input signal has said logic one and said logic zero levels, respectively; a first MOS transistor having a first gate terminal connected to an output of said first inverter, a first source terminal supplied with said predetermined positive voltage, and a first drain terminal connected to said output terminal and having a first channel between said first source and said first drain terminals, said first MOS transistor being put into a first source-drain conductive state to supply said predetermined positive voltage to said output terminal and to make a first source-drain current flow through said first channel when said inverted signal has one of said logic and said logic one levels, said first channel having a first predetermined width in order to restrict said first source-drain current within a predetermined value; a second MOS transistor having a second gate terminal connected to an output of said first inverter, a second source terminal which is grounded, and a second drain terminal connected to said output terminal and having a second channel between said second source and said second drain terminals, said second MOS transistor being put into a second source-drain conductive state in order to supply said ground potential to said output terminal when said inverted signal has the other one of said logic zero and said logic one levels, said second channel having said predetermined width; a subsidiary drive circuit which is grounded and which is supplied with said input signal, said output signal, and said predetermined positive voltage for driving said load circuit by one of said predetermined positive voltage and said ground potential during a transition time interval each time when said input signal changes from one of said logic one and zero levels to another of said logic one and zero levels; and supply means for supplying said output signal to said subsidiary drive circuit.

Claim 3

A driving circuit including an input terminal supplied with an input signal having one of logic one and zero levels and an output terminal for driving a load circuit connected to said output terminal in response to an output signal having one of a predetermine positive voltage and a ground potential said driving circuit comprising: a first inverter connected to said input terminal for inverting said input signal to produce a first inverted signal having logic zero and logic one levels when said input signal has said logic one and said logic zero levels, respectively; a first MOS transistor having a first gate terminal connected to an output of said first inverter, a first source terminal supplied with said predetermined positive voltage, and a first drain terminal connected to said output terminal and having a first channel between said first source and said first drain terminals, said first MOS transistor being put into a first source-drain conductive state to supply said predetermined positive voltage to said output terminal and to make a first source-drain current flow through said first channel when said inverted signal has one of said logic and said logic one levels, said first channel having a first predetermined width in order to restrict said first source-drain current within a predetermined value; a second MOS transistor having a second gate terminal connected to an output of said first inverter, a second source terminal which is grounded, and a second drain terminal connected to said output terminal and having a second channel between said second source and said second drain terminals, said second MOS transistor being put into a second source-drain conductive state in order to supply said ground potential to said output terminal when said inverted signal has the other one of said logic zero and said logic one levels, said second channel having said predetermined width; a subsidiary drive circuit which is grounded and which is supplied with said input signal, said output signal, and said predetermined positive voltage for driving said load circuit by one of said predetermined positive voltage and said ground potential during a transition time interval each time when said input signal changes from one of said logic one and zero levels to another of said logic one and zero levels; supply means for supplying said output signal to said subsidiary drive circuit; wherein said subsidiary drive circuit comprises a second inverter supplied with said output signal through said supply means for inverting said output signal to produce a second inverted signal having logic zero and one levels when said output terminal is supplied with said predetermined positive voltage and said ground potential, respectively; a NAND gate circuit having a first NAND input terminal supplied with said input signal and a second NAND input terminal connected to an output of said second inverter for producing a NAND output signal; a NOR gate circuit having a first NOR input terminal supplied with said input signal and a second NOR input terminal connected to an output of said second inverter for producing a NOR output signal; a third MOS transistor having a third gate terminal supplied with said NAND output signal, a third source terminal supplied with said predetermined positive voltage, and a third drain terminal connected to said output terminal and having a third channel between said third source and said third drain terminals; and a fourth MOS transistor having a fourth gate terminal supplied with said NOR output signal, a fourth source terminal which is grounded, and a fourth drain terminal connected to said output terminal and having a fourth channel between said fourth source and said fourth drain terminals, each of said third and said fourth channels having a prescribed width that is wider than said predetermined width.

Claim 4

A driving circuit including an input terminal supplied with an input signal having one of logic one and zero levels and an output terminal for driving a load circuit connected to said output terminal in response to an output signal having one of a predetermine positive voltage and a ground potential said driving circuit comprising: a first inverter connected to said input terminal for inverting said input signal to produce a first inverted signal having logic zero and logic one levels when said input signal has said logic one and said logic zero levels, respectively; a first MOS transistor having a first gate terminal connected to an output of said first inverter, a first source terminal supplied with said predetermined positive voltage, and a first drain terminal connected to said output terminal and having a first channel between said first source and said first drain terminals, said first MOS transistor being put into a first source-drain conductive state to supply said predetermined positive voltage to said output terminal and to make a first source-drain current flow through said first channel when said inverted signal has one of said logic and said logic one levels, said first channel having a first predetermined width in order to restrict said first source-drain current within a predetermined value; a second MOS transistor having a second gate terminal connected to an output of said first inverter, a second source terminal which is grounded, and a second drain terminal connected to said output terminal and having a second channel between said second source and said second drain terminals, said second MOS transistor being put into a second source-drain conductive state in order to supply said ground potential to said output terminal when said inverted signal has the other one of said logic zero and said logic one levels, said second channel having said predetermined width; a subsidiary drive circuit which is grounded and which is supplied with said input signal, said output signal, and said predetermined positive voltage for driving said load circuit by one of said predetermined positive voltage and said ground potential during a transition time interval each time when said input signal changes from one of said logic one and zero levels to another of said logic one and zero levels; supply means for supplying said output signal to said subsidiary drive circuit; wherein said subsidiary drive circuit comprises a second inverter supplied with said output signal through said supply means for inverting said output signal to produce a second inverted signal having logic zero and one levels when said output terminal is supplied with said predetermined positive voltage and said ground potential, respectively; a NAND gate circuit having a first NAND input terminal supplied with said input signal and a second NAND input terminal connected to an output of said second inverter for producing a NAND output signal; a NOR gate circuit having a first NOR input terminal supplied with said input signal and a second NOR input terminal connected to an output of said second inverter for producing a NOR output signal; a third MOS transistor having a third gate terminal supplied with said NAND output signal, a third source terminal supplied with said predetermined positive voltage, and a third drain terminal connected to said output terminal and having a third channel between said third source and said third drain terminals; and a fourth MOS transistor having a fourth gate terminal supplied with said NOR output signal, a fourth source terminal which is grounded, and a fourth drain terminal connected to said output terminal and having a fourth channel between said fourth source and said fourth drain terminals, each of said third and said fourth channels having a prescribed width that is wider than said predetermined width.