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US5173771A
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Motion detecting circuit for video image
Assignee: Sony Corp
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Filing: 1990-08-28
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Granted: 1992-12-22
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Expires: 2010-08-28
Abstract
Abstract A motion detecting circuit separates picture data of one frame into a plurality of image segments. The circuit includes a first memory for receiving picture data of current frame image and a second memory for receiving picture data of a previous or one frame delayed image. Each of the first and second memories comprises a plurality of memory areas separated into two blocks, and each individual memory area is adapted to store picture data for one image segment. The two memory blocks are operative in alternating fashion in reading and writing picture data. A plurality of arithmetic circuits are associated with the memory area to receive therefrom the picture data of each image segment and to process the received picture data for deriving a motion vector of each individual image segment.
Inventors
- 👤 Naohisa Kitazato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:21
CPC Classifications
G; G06; G06T; G06T7/00; G06T7/20; H; H04; H04N; H04N19/00; H04N19/42; H04N19/43; H04N19/433; G06T7/223; G06T7/238; H04N19/50; H04N19/503; H04N19/51
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
122 words
A motion detecting circuit for a video image comprising: a first buffer memory storing picture data of a current image, said picture data being separated into a plurality of first component data representative of plural current image segments; a second buffer memory storing picture data of a previous image, said picture data being separated into a plurality of second component data representative of plural previous image segments corresponding to said current image segments; and a plurality of arithmetic means for deriving a plurality of motion vectors for all of said segments, each of said arithmetic means receiving first component data and corresponding second component data for deriving vector data, and each of said arithmetic means receiving data representative of different individual segments.
Claim 2
Dependent Claim
122 words
A motion detecting circuit for a video image comprising: a first buffer memory storing picture data of a current image, said picture data being separated into a plurality of first component data representative of plural current image segments; a second buffer memory storing picture data of a previous image, said picture data being separated into a plurality of second component data representative of plural previous image segments corresponding to said current image segments; and a plurality of arithmetic means for deriving a plurality of motion vectors for all of said segments, each of said arithmetic means receiving first component data and corresponding second component data for deriving vector data, and each of said arithmetic means receiving data representative of different individual segments.
Claim 3
Dependent Claim
32 words
A motion detecting circuit as set forth in claim 1, wherein each of said arithmetic means comprises an absolute differential value calculating means, an accumulating circuit and a minimum value detecting circuit.
Claim 4
Dependent Claim
34 words
A motion detecting circuit as set forth in claim 1, wherein said first buffer memory stores data of the current frame image and said second buffer memory stores data of one frame delayed image.
Claim 5
Dependent Claim
32 words
A motion detecting circuit as set forth in claim 1, which further comprises a multiplexer connected to outputs of the plural arithmetic means, and an output buffer memory connected to the multiplexer.
Claim 6
Dependent Claim
72 words
A motion detecting circuit as set forth in claim 4, which further comprises a first address change-over circuit connected to said first and second buffer memories, for selectively controlling reading of data representative of one segment from said first and second buffer memories while simultaneously controlling writing of data representative of a different segment, and a second address change-over circuit connected to the output buffer memory for controlling reading and writing thereof.
Claim 7
Dependent Claim
38 words
A motion detecting circuit as set forth in claim 5, which further comprises a controller connected to said first and second change-over circuits, for selectively controlling reading and writing of said first and second and output buffer memories.
Claim 8
Dependent Claim
35 words
A motion detecting circuit as set forth in claim 6, wherein said controller is supplied with a synchronization signal which synchronizes operation of said first and second and output buffer memories with a video signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-22 | 1996-06-22 | 1996-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-22 | 2000-06-22 | 2000-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-22 | 2004-06-22 | 2004-12-22 | $7700.00 | Window Closed / Lapsed |