Sigma delta converter insensitive to asymmetrical switching times

Claim 2

Sigma-delta converter for converting an analog input signal into a sigma-delta code including a threshold device (222) for generating an output and feedback signal, a filter (214, 220) receiving said analog input signal and said output and feedback signal by means of at least one feedback loop, characterized in that it further includes: means (215, 221) located in said at least one feedback loop for performing a return-to-specified-logical-state of the sigma-delta code generated by said threshold device at every period of the sigma delta clock whereby said sigma-delta converter is insensitive to the asymmetry of the rise and fall times of said threshold device and further including: means (204, 206, 205, 207) for varying the duration of said return-to-zero thereby introducing an amplification step into the sigma-delta conversion process.

Claim 3

Sigma delta converter according to claim 5 characterized in that it includes: a first integrator (214, 213, 211, 212) receiving said analog input signal to be converted and a first feedback signal coming from a first said feedback loop, a second integrator (220, 217, 218, 219) receiving the analog output of said first integrator and a second feedback signal coming from a second said feedback loop and having an output lead connected to said threshold device, first means (215, 208) for performing a return-to-zero of the feedback signal conveyed through said first feedback loop to said first integrator and further including: a latch (222) clocked by a sigma-delta clock (sclk) and generating a sigma-delta code at a first output lead and an inverted sigma-delta code at a second output lead, said first integrator (214, 211, 212, 213) receiving the analog input signal to be converted and a first feedback signal coming from a first NOR gate (215) having a first input connected to said clock and a second input connected to said first output of said latch (222), said second integrator (220, 217, 218, 219) receiving the output signal of said first integrator and a second feedback signal coming from a second NOR gate (221) having a first input receiving said clock and a second input connected to said second output of said latch (222).

Claim 4

Sigma-delta converter according to claim 2 characterized in that said first integrator includes a first operational amplifier (214) having a inverting input connected to a first resistor (211) receiving said analog input signal to be converted, to a second resistor (212) connected to the output of said first NOR gate (215), and to a first lead of a capacitor (213) having a second lead connected to the output of said first operational amplifier, said operational amplifier having a non-inverting input connected to a reference potential.

Claim 5

Sigma-delta converter according to claim 3 characterized in that said second integrator includes a second operational amplifier (220) having an inverting input connected to a third resistor (217) also connected to the output of said first operational amplifier, to a fourth resistor (218) connected to the output of said second NOR gate (221), and to a first lead of a second capacitor (219) having a second lead connected to the output of said second operational amplifier, said operational amplifier having a non-inverting input connected to said reference potential (Vref).