← Back to Patent Explorer
US5198997A Expired / Lapsed US ⏱️ 0.0 years remaining

Ultraviolet erasable nonvolatile memory with current mirror circuit type sense amplifier

Assignee: Sony Corp
•
Filing: 1992-01-08
•
Granted: 1993-03-30
•
Expires: 2012-01-08
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An ultraviolet erasable nonvolatile memory device comprising a plurality of memory cells which are erasable by ultraviolet rays employs a sense amplifier consisting a current mirror circuit. The current mirror circuit is connected to the memory cells and a reference cell respectively for readout. In one example, an effective control gate voltage of the reference cell is set to a lower value than that of the memory cells. The current drivability of the reference cell exhibits an intermediate value between that of erased memory cell and that of programmed memory cell. In another example, a constant current source is provided at a node between the memory cells and the current mirror circuit, so that a current on the reference cell side is subtracted by the constant current source.

Inventors

  • 👤 Hideki Arakawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 20:44
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C16/10; G11C16/18

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 188 words
A nonvolatile memory device comprising: a plurality of memory cells of a first conductivity type for storing data, a reference cell having the same structure and the same first conductivity type as said memory cells, a sense amplifier comprising a first MIS transistor of a second conductivity type, a second MIS transistor having the same structure and the same second conductivity type as said first MIS transistor, wherein said gate and drain electrodes of said first MIS transistor are connected to a first node and said gate electrode of said second MIS transistor is connected to said first node and said drain electrode of said second MIS transistor is connected to a second node, and said reference cell is connected between said first node and a ground node, and said memory cell is connected between said second node and ground note; and a constant current source connected between said second node and ground node, wherein the current drivability of said current source has an intermediate value between a value of the current drivability in an erased state and a value of the current drivability in a programmed state.
Claim 2
Dependent Claim 188 words
A nonvolatile memory device comprising: a plurality of memory cells of a first conductivity type for storing data, a reference cell having the same structure and the same first conductivity type as said memory cells, a sense amplifier comprising a first MIS transistor of a second conductivity type, a second MIS transistor having the same structure and the same second conductivity type as said first MIS transistor, wherein said gate and drain electrodes of said first MIS transistor are connected to a first node and said gate electrode of said second MIS transistor is connected to said first node and said drain electrode of said second MIS transistor is connected to a second node, and said reference cell is connected between said first node and a ground node, and said memory cell is connected between said second node and ground note; and a constant current source connected between said second node and ground node, wherein the current drivability of said current source has an intermediate value between a value of the current drivability in an erased state and a value of the current drivability in a programmed state.
Claim 3
Dependent Claim 21 words
The ultraviolet erasable nonvolatile memory device according to claim 1, wherein the constant current source is a depletion type MOS transistor.
Claim 4
Dependent Claim 47 words
The ultraviolet erasable nonvolatile memory device according to claim 1, wherein an inverter connected to said node amplifies the potential of said node, and a input terminal and a output terminal of said inverter are connected each other by a switching means before data outputting operation. d

References Cited (Backward Citations)

US4611301A Cited
US4916665A Cited
US4799195A Cited
US4843594A Cited
US4713797A Cited
US4819212A Cited
US5022003A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-03-29 1996-09-28 1997-03-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-03-29 2000-09-28 2001-03-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-03-29 2004-09-28 2005-03-30 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag