Redundancy circuit for high speed EPROM and flash memory devices

Claim 1

A control circuit for enabling a reading operation of a plurality of redundant cells in a memory circuit, the memory circuit having an array of memory cells and a memory array decoding circuit coupled to said memory array and connectable to a plurality of addressing lines, said control circuit comprising: a redundant cell decoding circuit coupled to said plurality of redundant cells for providing a select signal to said redundant cells; an address select circuit coupled to said redundant cell decoding circuit and connectable to said plurality of addressing lines, said address select circuit including a first means for programming said address select circuit to provide an address select signal to said redundant cell decoding circuit in response to an address signal at said addressing lines; an enable-disable circuit coupled to said redundant cell decoding circuit having a second means for programming said enable-disable circuit to provide an enable signal to said redundant cell decoding circuit; wherein said first means for programming said address select circuit is a first programmable fuse circuit and wherein said means for programming said enable-disable circuit is a second programmable fuse circuit and wherein each of said first and second programmable fuse circuits include: a first programmable element; an enable input line coupled to said first programmable element for receiving a chip select pulse; and an output line coupled to said first programmable element; wherein a first voltage level is latched at said output line when said first programmable element is programmed in a first state, and wherein a second voltage level is latched at said output lien when said first programmable element is programmed in a second state.