US5204834A
Expired / Lapsed
US
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Static semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1991-05-24
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Granted: 1993-04-20
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Expires: 2011-05-24
Abstract
Abstract A plurality of static memory cells 10 each comprising a thin film transistor acting as a load are connected to a power source wiring 12 positioned within a memory cell array. The power source wiring 12 positioned within the memory cell array is connected via a resistor circuit 14 to a power source wiring 13 of a low resistivity, which is positioned outside the memory cell array.
Inventors
- 👤 Kiyofumi Ochii
- 👤 Shigeyuki Hayakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C5/00; G11C5/14; G11C5/147; G11C11/412
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
166 words
A static semiconductor memory device, comprising a memory cell array consisting of a plurality of memory cells each having a data memory node and a thin film transistor used as a load transistor and connected to one end of the memory node; a first power source wiring arranged within the memory cell array, and connected to each memory cell so as to supply a power source potential to each memory cell; a second power source wiring of a low resistance to which a power source potential is supplied from the outside and which is electrically connected to the first power source wiring; and circuit means satisfying the relationship τ 2≧τ 1 wherein τ 1 denotes a time constant in the case of charging/discharging the memory node of each memory cell by the first power source wiring, and τ 2 represents a time constant in the case of charging/discharging the first power source wiring by the external power source potential supplied to the second power source wiring.
Claim 2
Dependent Claim
166 words
A static semiconductor memory device, comprising a memory cell array consisting of a plurality of memory cells each having a data memory node and a thin film transistor used as a load transistor and connected to one end of the memory node; a first power source wiring arranged within the memory cell array, and connected to each memory cell so as to supply a power source potential to each memory cell; a second power source wiring of a low resistance to which a power source potential is supplied from the outside and which is electrically connected to the first power source wiring; and circuit means satisfying the relationship τ 2≧τ 1 wherein τ 1 denotes a time constant in the case of charging/discharging the memory node of each memory cell by the first power source wiring, and τ 2 represents a time constant in the case of charging/discharging the first power source wiring by the external power source potential supplied to the second power source wiring.
Claim 3
Dependent Claim
31 words
The static semiconductor memory device according to claim 1, wherein said first power source wiring is formed of a polycrystalline silicon, and said second power source wiring is formed of aluminum.
Claim 4
Dependent Claim
38 words
The static semiconductor memory device according to claim 1, wherein said circuit means satisfying the relationship τ 2≧τ 1 is formed of a resistance circuit interposed between the first power source wiring and the second power source wiring.
Claim 5
Dependent Claim
33 words
The static semiconductor memory device according to claim 2, wherein said resistance circuit is formed of a transistor equivalent to the thin film transistor used as a load transistor in each memory cell.
Claim 6
Dependent Claim
19 words
The static semiconductor memory device according to claim 2, wherein said resistance circuit is formed of a resistance element.
Claim 7
Dependent Claim
36 words
The static semiconductor memory device according to claim 2, wherein said resistance circuit is formed of an enhancement type MOS transistor having the gate supplied with a predetermined bias voltage, said transistor being always kept conductive.
Claim 8
Dependent Claim
86 words
A static semiconductor memory device, comprising a memory cell array consisting of a plurality of memory cells each having a data memory node and a thin film transistor used as a load transistor and connected to one end of the memory node; a power source wiring connected to each memory cell included in the memory cell array so as to supply a power source potential to each memory cell; and a capacitor connected between the memory node of each memory cell and said power source wiring.
Claim 9
Dependent Claim
86 words
A static semiconductor memory device, comprising a memory cell array consisting of a plurality of memory cells each having a data memory node and a thin film transistor used as a load transistor and connected to one end of the memory node; a power source wiring connected to each memory cell included in the memory cell array so as to supply a power source potential to each memory cell; and a capacitor connected between the memory node of each memory cell and said power source wiring.
Claim 10
Dependent Claim
55 words
The static semiconductor memory device according to claim 7, wherein the capacitance of the capacitor is set to meet said relationship Vcc-Vnod≦Vth, where Vcc denotes the potential at said power source wiring, Vnod represents the potential at said memory node for each memory cell, and Vth is the threshold voltage of said thin film transistor.
Claim 11
Dependent Claim
75 words
The static semiconductor memory device according to claim 7, wherein one of the electrodes included in said capacitor is provided by a first conductive layer forming the gate of the thin film transistor and the other electrode of the capacitor is provided by a second conductive layer in which is formed the channel of a thin film transistor, said second conductive layer being superposed on the first conductive layer with an insulating layer interposed therebetween.
Claim 12
Dependent Claim
62 words
The static semiconductor memory device according to claim 7, wherein one of the electrodes included in said capacitor is provided by a first conductive layer in which is formed the channel of a thin film transistor, and the other electrode of the capacitor is provided by a second conductive layer superposed on the first conductive layer with an insulating layer interposed therebetween.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |