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US5204841A
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Virtual multi-port RAM
Assignee: International Business Machines Corp
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Filing: 1992-04-23
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Granted: 1993-04-20
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Expires: 2012-04-23
Abstract
Abstract A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
Inventors
- 👤 Barbara A. Chappell
- 👤 Terry I. Chappell
- 👤 Mahmut K. Ebcioglu
- 👤 Stanley E. Schuster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:24
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G06; G06F; G06F12/00; G06F12/02; G06F12/04; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G11C8/12; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
533 words
A RAM structure allowing multiple read and write accesses during a machine cycle, said RAM structure being implemented on a semiconductor chip as an array of single-port static RAM cells, said array being divided into one or more sub-arrays, comprising for each sub-array; means in the sub-array for generating a release next address signal when a RAM cell within the sub-array has been written or read; an on-chip clock circuit responsive to a chip select signal to generate a trigger signal to initiate a first access to said sub-array; a plurality of address lines connected to a plurality of address buffers which receive and temporarily store one or more addresses in response to said trigger signal; a plurality of address latches connected to receive an output from a corresponding one of said address buffers; first circuit means responsive to said release next address signal and to said trigger signal for generating a set-up next signal to said address latches in succession; address bus drivers connected to receive an address signal output from any of the address latches for which a set-up next signal has been generated by said first circuit means and in response to said release next address signal from said sub-array, said address bus drivers providing said address signal on an address bus; decoder and driver circuit means connected to receive the address signal from said address bus for generating sub-array select, column, wordline, and bitline signals to said sub-array, said decoder and driver circuit means being self-resetting; a plurality of data input lines connected to a plurality of data-in buffers which receive and temporarily store one or more data input words in response to said trigger signal; a plurality of data-in latches connected to receive an output from a corresponding one of said data-in buffers; second circuit means responsive to said trigger signal for generating a set-up next signal to said data-in latches in succession, said second circuit means receiving a release next data-in signal which is derived from said release next address signal; data-in bus drivers connected to receive a data-in signal output from any of the data-in latches for which a set-up next signal has been generated by said second circuit means and in response to said release next data-in signal, said data-in bus drivers providing the data-in signal on a data-in bus connected to a write input of the sub-array; a plurality of sense amplifiers in the sub-array to output data read out of RAM cells, said plurality of sense amplifiers being connected to a corresponding one of a plurality of data output lines; a data-out bus connected to said data output lines to receive data read out of said sub-array; a plurality of data-out latches connected to receive data output on said data-out bus, said latches including self-resetting circuit means for resetting a latch upon the latch outputting a data-out signal; third circuit means responsive to said trigger signal for generating a set-up next signal to said data-out latches in succession; and a plurality of off-chip driver circuits each connected to receive an output from a corresponding one of said data-out latches for which a set-up next signal has been generated by said third circuit means.
Claim 2
Dependent Claim
533 words
A RAM structure allowing multiple read and write accesses during a machine cycle, said RAM structure being implemented on a semiconductor chip as an array of single-port static RAM cells, said array being divided into one or more sub-arrays, comprising for each sub-array; means in the sub-array for generating a release next address signal when a RAM cell within the sub-array has been written or read; an on-chip clock circuit responsive to a chip select signal to generate a trigger signal to initiate a first access to said sub-array; a plurality of address lines connected to a plurality of address buffers which receive and temporarily store one or more addresses in response to said trigger signal; a plurality of address latches connected to receive an output from a corresponding one of said address buffers; first circuit means responsive to said release next address signal and to said trigger signal for generating a set-up next signal to said address latches in succession; address bus drivers connected to receive an address signal output from any of the address latches for which a set-up next signal has been generated by said first circuit means and in response to said release next address signal from said sub-array, said address bus drivers providing said address signal on an address bus; decoder and driver circuit means connected to receive the address signal from said address bus for generating sub-array select, column, wordline, and bitline signals to said sub-array, said decoder and driver circuit means being self-resetting; a plurality of data input lines connected to a plurality of data-in buffers which receive and temporarily store one or more data input words in response to said trigger signal; a plurality of data-in latches connected to receive an output from a corresponding one of said data-in buffers; second circuit means responsive to said trigger signal for generating a set-up next signal to said data-in latches in succession, said second circuit means receiving a release next data-in signal which is derived from said release next address signal; data-in bus drivers connected to receive a data-in signal output from any of the data-in latches for which a set-up next signal has been generated by said second circuit means and in response to said release next data-in signal, said data-in bus drivers providing the data-in signal on a data-in bus connected to a write input of the sub-array; a plurality of sense amplifiers in the sub-array to output data read out of RAM cells, said plurality of sense amplifiers being connected to a corresponding one of a plurality of data output lines; a data-out bus connected to said data output lines to receive data read out of said sub-array; a plurality of data-out latches connected to receive data output on said data-out bus, said latches including self-resetting circuit means for resetting a latch upon the latch outputting a data-out signal; third circuit means responsive to said trigger signal for generating a set-up next signal to said data-out latches in succession; and a plurality of off-chip driver circuits each connected to receive an output from a corresponding one of said data-out latches for which a set-up next signal has been generated by said third circuit means.
Claim 3
Dependent Claim
44 words
The RAM structure recited in claim 1 wherein said each of said plurality of address latches and each of said plurality of data-in latches include self-resetting circuit means for resetting a latch upon the latch outputting an address signal or a data-in signal, respectively.
Claim 4
Dependent Claim
167 words
The RAM structure recited in claim 1 wherein said first circuit means are included in and distributed among said plurality of address latches so that all of said address latches are responsive to said release next address signal, said first circuit means in an address latch generating said set-up next signal to a succeeding address latch upon the latch outputting an address signal to said address bus drivers, said second circuit means are included in and distributed among said plurality of data-in latches so that all of said data-in latches are responsive to said release next data-in signal, said second circuit means in a data-in latch generating said set-up next signal to a succeeding data-in latch upon the latch outputting a data-in signal to said data-in bus drivers, and said third circuit means are included in and distributed among said data-out latches, said third circuit means in a data-out latch generating said set-up next signal to a succeeding data-out latch upon the latch outputting a data-out signal.
Claim 5
Dependent Claim
94 words
The RAM structure recited in claim 3 wherein said address bus includes first cycle circuit means for resetting, precharging and holding said bus ready for a next cycle upon outputting an address signal to said decoder and driver circuit means, said data-in bus includes second cycle circuit means for resetting, precharging and holding said bus ready for a next cycle upon outputting a data-in signal to said sub-array, and said data-out bus includes cycle circuit means for resetting, precharging and holding said data-out bus ready for a next cycle upon outputting a data-out signal.
Claim 6
Dependent Claim
178 words
The RAM structure recited in claim 1 further including sequence data input means for receiving sequence bits defining a sequence order and wherein said first circuit means is connected to said on-chip clock circuit and responsive to said trigger signal and said release next address signal and includes address sequence logic means for receiving said sequence bits and generating said set-up next signal to address latches according to said sequence order upon a latch outputting an address signal to said address bus drivers, said second circuit means is responsive to said trigger signal and said next data-in signal and includes data-in sequence logic means for receiving said sequence bits and generating said set-up next signal to data-in latches according to said sequence order upon a latch outputting a data-in signal to said data-in bus drivers, and said third circuit means is responsive to said trigger signal and includes data-out sequence logic means for receiving said sequence bits and generating said set-up next signal to data-out latches according to said sequence order upon the latch outputting a data-out signal.
Claim 7
Dependent Claim
94 words
The RAM structure recited in claim 5 wherein said address bus includes first cycle circuit means for resetting, precharging and holding said bus ready for a next cycle upon outputting an address signal to said decoder and driver circuit means, said data-in bus includes second cycle circuit means for resetting, precharging and holding said bus ready for a next cycle upon outputting a data-in signal to said sub-array, and said data-out bus includes cycle circuit means for resetting, precharging and holding said data-out bus ready for a next cycle upon outputting a data-out signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |