Semiconductor memory device having bit lines and word lines different in data reading and data writing

Claim 2

A semiconductor memory device comprising: a plurality of memory cells (1) arranged in a plurality of columns, a plurality of reading bit lines (4) each corresponding to a respective one of said columns, selecting means (9) for selecting one of said reading bit lines (4) for a predetermined time period, precharging means (7) corresponding to each of said reading bit lines (4) for precharging said bit lines (4), first activating means (9) for activating the precharging means (7) corresponding to the selected bit line for a predetermined portion of said predetermined time of period, switching means (8) connected to said bit lines (4) for extracting the potential on said corresponding reading bit line (4), and second activating means (9) for activating said switching means (8) during said predetermined time period and subsequent to said predetermined portion.

Claim 3

A semiconductor memory device as recited in claim 1, wherein said selecting means (9) comprises means for sequentially changing the reading bit line (4) selection.

Claim 4

A semiconductor memory device as recited in claim 1, wherein said selecting means (9) comprises shift register means (F0-Fn) and logic circuit means (G0-Gn, NR0-NRn) for generating signals to activate said first and second activating means (9).

Claim 5

The semiconductor memory device as recited in claim 3, wherein said selecting means (9) comprises: first signal applying means (F0-Fn, G0-Gn) for applying first signals for designating said predetermined portion, second signal applying means (F0-Fn, NR0-NRn) for applying second signals for designating a portion subsequent to said predetermined portion and during said predetermined time period, said first activating means (9) shares said first signal applying means (F0-Fn, G0-Gn) with said selecting means (9), said second activating means (9) shares said second signal applying means (F0-Fn, NR0-NRn) with said selecting means (9).

Claim 6

The semiconductor memory device as recited in claim 4, wherein said selecting means (9) sequentially selects one of said reading bit lines (4) for every said predetermined time period.

Claim 7

The semiconductor memory device as recited in claim 5, wherein said first signal applying means (F0-Fn, G0-Gn) sequentially applies said first signal to one of said precharging means (7) for every said predetermined time period, said second signal applying means (F0-Fn, NR0-NRn) sequentially applies said second signal to one of said switching means (8) for every said predetermined time period at a timing delayed from said first signal applying means by a time period corresponding to said portion.

Claim 8

A semiconductor memory device as recited in claim 1, wherein said precharging means (7) comprises a semiconductor switching device (7) connected between each reading bit line (4) and a power supply (Vcc).

Claim 9

The semiconductor memory device as recited in claim 7, wherein a polarity of said semiconductor switching device (7) is N type.

Claim 10

The semiconductor memory device as recited in claim 4, wherein each of said switching means (8) includes a semiconductor switching device (8) having a first conduction terminal connected to the corresponding reading bit line (4), a second conduction terminal and a control terminal for receiving said second signal.

Claim 11

The semiconductor memory device as recited in claim 9, wherein the polarity of said semiconductor switching device (8) is N type.

Claim 12

The semiconductor memory device as recited in claim 4, wherein the logical level of said first signal and the logical level of said second signal are the same.

Claim 13

The semiconductor memory device as recited in claim 5, wherein said shift register means includes the same number of flip-flop means (F0-Fn), each of said flip-flop means (F0-Fn) being controlled by an external clock signal to apply first and second output signals having logical levels complementary from each other, said logic circuit means (NR0-NRn, G0-Gn) comprises first logic gate means (G0-Gn) provided corresponding to said respective flip-flops (F0-Fn) and second logic gate means (NR0-NRn) provided corresponding to said respective flip-flop means (F0-Fn), each of said first logic gate means (G0-Gn) receiving said first output signal of the corresponding one of said flip-flop means (F0-Fn) and said external clock signal to output said first signal, each of said second logic gate means (NR0-NRn) receiving said second output signal of the corresponding one of said flip-flop means (F0-Fn) and said external clock signal to output said second signal, said first signal applying means (F0-Fn, G0-Gn) includes said flip-flop means (F0-Fn) and said first logic gate means (G0-Gn), said second signal applying means (F0-Fn, NR0-NRn) includes said flip-flop means (F0-Fn) and said second logic gate means.

Claim 14

The semiconductor memory device as recited in claim 12, wherein said first logic gate means (G0-Gn) includes two-input AND gates (G0-Gn) and said second logic gate means (NR0-NRn) includes two-input NOR gates (NR0-NRn).

Claim 15

A semiconductor memory device comprising: a plurality of memory cells (1) arranged in a plurality of columns, a plurality of reading bit lines (4) each corresponding to said respective one of said columns, selecting means (114) for selecting one of said reading bit lines for a predetermined period, precharging means (7) corresponding to each of said reading bit lines (4) for precharging said corresponding reading bit lines, and activating means (114) for activating one of said precharging means (7) corresponding to the selected reading bit line for only said predetermined period.

Claim 16

A semiconductor memory device comprising: a plurality of memory cells (1) arranged in a plurality of columns, a plurality of reading bit lines (4) each corresponding to said respective one of said columns, selecting means (114) for selecting one of said reading bit lines for a predetermined period, precharging means (7) corresponding to each of said reading bit lines (4) for precharging said corresponding reading bit lines, and activating means (114) for activating one of said precharging means (7) corresponding to the selected reading bit line for only said predetermined period.

Claim 17

The semiconductor memory device as recited in claim 14, wherein said selecting means (114) sequentially selects one of said reading bit lines.

Claim 18

The semiconductor memory device as recited in claim 14, wherein said selecting means (114) and said activating means (114) commonly comprise signal applying means (114) for applying a signal for designating said predetermined period and selectively one of said reading bit lines (4).

Claim 19

The semiconductor memory device as recited in claim 14, wherein said selecting means (114) sequentially selects one of said reading bit lines (4).

Claim 20

The semiconductor memory device as recited in claim 16, wherein said signal applying means (114) sequentially applies said designating signal to one of said precharging means (7).

Claim 21

A semiconductor memory devices as recited in claim 14, wherein said selecting means (114) comprises shift register means (F0-Fn) and logic circuit means (G0 -Gn).

Claim 22

The semiconductor memory device as recited in claim 16, wherein each of said precharging means (7) includes a semiconductor switching means (7) having a control terminal for receiving said designating signal, a first conduction terminal connected to the corresponding reading bit line (4) and a second conduction terminal connected to a power supply (19).

Claim 23

The semiconductor memory device as recited in claim 20, wherein the polarity of said semiconductor switching means (7) is N type and the logical level of said designating signal is a "H" level.

Claim 24

The semiconductor memory device as recited in claim 18, wherein said shift register mean includes flip-flop means (F0 -Fn) of the same number as that of said columns which are connected in series, said logic circuit means includes logic gate means (G0-Gn) provided corresponding to said respective flip-flop means (F0-Fn), each of said logic gate means (G0-Gn) receiving the output of the corresponding one of flip-flop means (F0-Fn) and an external clock signal to output said designating signal, said signal applying means (114) includes said flip-flop means (F0-Fn) and said logic gate means (G0-Gn).

Claim 25

The semiconductor memory device as recited in claim 22, wherein said logic gate means (G0-Gn) include two-input AND gates (G0-Gn).

Claim 26

A serial access semiconductor memory device comprising: a plurality of memory cells (1) arranged in a matrix of rows and columns, a writing word line (5) corresponding to each row of memory cells (1) and a writing bit line (3) corresponding to each column of memory cells (1) for selectively writing information to said memory cells (1); a reading word line (6) corresponding to each row of memory cells (1) and a reading bit line (4) corresponding to each column of memory cells (1) for selectively reading information from said memory cells (1), each memory cell (1) comprising a writing transistor (14), a storage capacitor (17), a storage transistor (15) and a reading transistor (16), selecting means (9) for sequentially selecting one of said reading bit lines (4) for a predetermined time period, precharging means (7) corresponding to each of said reading bit lines (4) for precharging said bit lines (4), first activating means (9) for activating the precharging means (7) corresponding to the selected bit line for a predetermined portion of said predetermined time period, switching means (8) connected to said bit lines (4) for extracting the potential on said corresponding reading bit line (4), and second activating means (9) for activating said switching means (8) during said predetermined time period and subsequent to said predetermined portion.

Claim 27

A serial access semiconductor memory device comprising: a plurality of memory cells (1) arranged in a matrix of rows and columns, a writing word line (5) corresponding to each row of memory cells (1) and a writing bit line (3) corresponding to each column of memory cells (1) for selectively writing information to said memory cells (1); a reading word line (6) corresponding to each row of memory cells (1) and a reading bit line (4) corresponding to each column of memory cells (1) for selectively reading information from said memory cells (1), each memory cell (1) comprising a writing transistor (14), a storage capacitor (17), a storage transistor (15) and a reading transistor (16), selecting means (9) for sequentially selecting one of said reading bit lines (4) for a predetermined time period, precharging means (7) corresponding to each of said reading bit lines (4) for precharging said bit lines (4), first activating means (9) for activating the precharging means (7) corresponding to the selected bit line for a predetermined portion of said predetermined time period, switching means (8) connected to said bit lines (4) for extracting the potential on said corresponding reading bit line (4), and second activating means (9) for activating said switching means (8) during said predetermined time period and subsequent to said predetermined portion.

Claim 28

A semiconductor memory device as recited in claim 24, wherein said switching means (8) comprises transistor means directly connected to each reading bit line (4), and further comprising reading data buffer means (104) directly connected to said switching means (8) for reading information from a selected bit line.

Claim 29

A serial access semiconductor memory device comprising: a plurality of memory cells (1) arranged in a matrix of rows ad columns; a writing word line (5) corresponding to each row of memory cells (1) and a writing bit line (3) corresponding to each column of memory cells (1) for selectively writing information to said memory cells (1); a reading word line (6) corresponding to each row of memory cells (1) and a reading bit line (4) corresponding to each column of memory cells (1) for selectively reading information from said memory cells (1), each memory cell (1) comprising a writing transistor (14), a storage capacitor (17), a storage transistor (15) and a reading transistor (16), selecting means (114) for sequentially selecting one of said reading bit lines (4) for a predetermined period, precharging means (7) corresponding to each of said reading bit lines (4) for precharging said corresponding reading bit lines (4) to a predetermined potential, and activating means (114) for activating one of said precharging means (7) corresponding to the selected read bit line only for said predetermined period.

Claim 30

A serial access semiconductor memory device comprising: a plurality of memory cells (1) arranged in a matrix of rows ad columns; a writing word line (5) corresponding to each row of memory cells (1) and a writing bit line (3) corresponding to each column of memory cells (1) for selectively writing information to said memory cells (1); a reading word line (6) corresponding to each row of memory cells (1) and a reading bit line (4) corresponding to each column of memory cells (1) for selectively reading information from said memory cells (1), each memory cell (1) comprising a writing transistor (14), a storage capacitor (17), a storage transistor (15) and a reading transistor (16), selecting means (114) for sequentially selecting one of said reading bit lines (4) for a predetermined period, precharging means (7) corresponding to each of said reading bit lines (4) for precharging said corresponding reading bit lines (4) to a predetermined potential, and activating means (114) for activating one of said precharging means (7) corresponding to the selected read bit line only for said predetermined period.

Claim 31

The semiconductor memory device as recited in claim 24, wherein each of said plurality of memory cells (1) comprises: a first field effect semiconductor element (14) connected to the corresponding one of said writing bit lines (3) and the corresponding one of said writing word lines (5), a second field effect semiconductor element (16) connected to the corresponding one of said reading bit lines (4) and the corresponding one of said reading word lines (6), a third field effect semiconductor element (15) provided between said first field effect semiconductor element (14) and said second field effect semiconductor element (16), a capacitance element (17) provided between said first field effect semiconductor element (14) and said third field effect semiconductor element (15).

Claim 32

The semiconductor memory device as recited in claim 26, wherein each of said plurality of memory cells (1) comprises: a first field effect semiconductor element (14) connected to the corresponding one of said writing bit lines (3) and the corresponding one of said writing word lines (5), a second field effect semiconductor element (16) connected to the corresponding one of said reading bit lines (4) and the corresponding one of said reading word lines (6), a third field effect semiconductor element (15) provided between said first field effect semiconductor element (14) and said second field effect semiconductor element (16), a capacitance element (17) provided between said first field effect semiconductor element (14) and said third field effect semiconductor element (15).

Claim 33

A semiconductor memory device comprising: a plurality of memory cells (1) arranged in a plurality of columns, reading bit lines (4) provided corresponding to said plurality of columns, selecting means (9,114) for selecting one said reading bit lines (4), and precharging means (7) provided corresponding to said respective reading bit lines (4) for precharging, only for a predetermined period, a corresponding reading bit line (4) to a predetermined potential when said corresponding reading bit line (4) is selected by said selecting means (9, 114).

Claim 34

A semiconductor memory device comprising: a plurality of memory cells (1) arranged in a plurality of columns, reading bit lines (4) provided corresponding to said plurality of columns, selecting means (9,114) for selecting one said reading bit lines (4), and precharging means (7) provided corresponding to said respective reading bit lines (4) for precharging, only for a predetermined period, a corresponding reading bit line (4) to a predetermined potential when said corresponding reading bit line (4) is selected by said selecting means (9, 114).

Claim 35

The semiconductor memory device as recited in claim 4, wherein each of said switching means includes a first semiconductor switching element and a second semiconductor switching element, said first and second semiconductor elements connected in parallel to each other and having complementary polarities.