Instruction generator architecture for a video signal processor controller

Claim 2

An instruction generator circuit having inputs for receiving operating mode signals from an external source and an output for supplying instructions to a video signal processing device having a plurality of one-bit parallel operating processor elements, each processor element having inputs for receiving the instructions and executing instruction in accordance with the corresponding control code and register address, each instruction consisting of a control code and a register address, the control code of at least one instruction indicating that instruction is a repeat instruction, the instruction generator circuit comprising: an instruction program memory having a plurality of instructions stored in addressable memory locations, said instruction program memory supplying an instruction including the control code and the register address at an instruction output in response to receipt of a corresponding address at an address input; a program counter connected to said address input of said instruction program memory and having a mode input receiving the operating mode signals from the external source, said program counter supplying an address to said address input of said instruction program memory corresponding to the received operation mode signal; a control code latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the control code of an instruction recalled from said instruction program memory and supplying the control code stored therein to the video signal processing device; a register output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the register address of an instruction recalled from said instruction program memory and supplying the register address stored therein to the video signal processing device; an instruction decoder circuit connected to said instruction output of said instruction program memory, said control code latch and said register address latch, said instruction decoder circuit for controlling said control code latch to again supply said control code stored therein to the video signal processing device and controlling said register address latch to increment the register address stored therein and supply the incremented register address to the video signal processing device upon detection that the control code of said instruction recalled from said instruction program memory indicates a repeat instruction.

Claim 3

The instruction generator circuit claimed in claim 1, wherein the at least one repeat instruction includes at least one first repeat instruction and at least one second repeat instruction, and wherein: said address decoder circuit controlling said register address latch to increment the register address stored therein by one upon detection that the control code of said instruction recalled from said instruction program memory indicates a first repeat instruction, and controlling said register address latch to increment the register address stored therein by two upon detection that the control code of said instruction recalled from said instruction program memory indicates a second repeat instruction.

Claim 4

The instruction generator circuit claimed in claim 1, further comprising: an auxiliary register memory having an external input connected to an external source and a control code input connected to said control code latch and a control code output connected to the video signal processing device, said auxiliary register memory supplying a predetermined portion of a control code corresponding to an external input instead of the predetermined portion of the control code stored in said control code latch upon detection of a predetermined external input and a predetermined control code received from said control code latch.

Claim 5

The instruction generator circuit claimed in claim 1, wherein the register address of each instruction including a first register address and a second register address, each processor element including a first register file responsive to a first register address and a second register file responsive to a second register address, wherein: said register address latch consists of a first register address latch receiving the first register address of each instruction and a second register address latch receiving the second register address of each instruction; and an instruction decoder circuit controls said register address latch to separately increment the first register address stored in said first register address latch and the second register address stored in the second register address latch.

Claim 6

The instruction generator circuit claimed in claim 4, wherein at least one instruction includes global rotation instruction, said instruction generator circuit further comprising: first and second global rotation address generators, each having an input connected to said output of a corresponding first and second register address latch, an output connected to the video signal processing device and a control input, said first and second global rotation address generators for modulus rotation of the corresponding register address according to a global rotation control received on said control input; and wherein said instruction decode circuit further includes a control output for generating a global rotation control thereon corresponding to the control code of an instruction upon detection that the control code of said instruction indicates a global rotation instruction.

Claim 7

The instruction generator circuit claimed in claim 1, wherein the video signal processing device receives an external video signal having a synchronizing signal, said instruction generator circuit further comprising: a synchronizing control circuit having a synchronizing input receiving the external video signal and coupled to said instruction program memory, said program counter, said control code latch, said register address latch and said address decoder circuit for synchronizing supply of the instructions to the video signal processing device to the synchronizing signal of the external video signal.

Claim 8

The instruction generator circuit claimed in claim 1, wherein each one repeat instruction includes an indication of a number of repeats within the control code, and wherein: said instruction decoder circuit controlling said control code latch to again supply said control code stored therein to the video signal processing device and controlling said register address latch to increment the register address stored therein and supply the incremented register address to the video signal processing device the number of repeats indicated within the control code of an instruction recalled from said instruction program memory upon detection that the control code of said instruction recalled from said instruction program memory indicates a repeat instruction.

Claim 9

A television receiving system for receiving a standard television transmission signal and producing a picture comprising: an analog to digital converter for converting the received standard television transmission signal into digital picture samples; a processor system having an input connected to said analog to digital converter for receiving said digital picture samples, an output for generating processed digital picture samples, said processor system including a plurality of one-bit parallel operating processor elements, each processor element having data inputs for receiving digital picture samples, instruction inputs for receiving the instructions and data outputs for generating digital picture samples, each processor element executing instructions converting digital picture samples into processed digital picture samples in accordance with the corresponding control code and register address, each instruction consisting of a control code and a register address, the control code of at least one instruction indicating that instruction is a repeat instruction, an instruction generator circuit including an instruction program memory having a plurality of instructions stored in addressable memory locations, said instruction program memory supplying an instruction including the control code and the register address at an instruction output in response to receipt of a corresponding address at an address input, a program counter connected to said address input of said instruction program memory and having a mode input receiving the operating mode signals from the external source, said program counter supplying an address to said address input of said instruction program memory corresponding to the received operation mode signal, a control code latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the control code of an instruction recalled from said instruction program memory and supplying the control code stored therein to the video signal processing device, a register address latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the register address of an instruction recalled from said instruction program memory and supplying the register address stored therein to the video signal processing device, an instruction decoder circuit connected to said instruction output of said instruction program memory, said control code latch and said register address latch, said instruction decoder circuit for controlling said control code latch to again supply said control code stored therein to the video signal processing device and controlling said register address latch to increment the register address stored therein and supply the incremented register address to the video signal processing device upon detection that the control code of said instruction recalled from said instruction program memory indicates a repeat instruction; a digital to analog converter connected to said processor system for converting said processed digital picture samples into an analog picture signal; a display unit connected to said digital to analog converter for generating a visual display corresponding to said analog picture signal.

Claim 10

A television receiving system for receiving a standard television transmission signal and producing a picture comprising: an analog to digital converter for converting the received standard television transmission signal into digital picture samples; a processor system having an input connected to said analog to digital converter for receiving said digital picture samples, an output for generating processed digital picture samples, said processor system including a plurality of one-bit parallel operating processor elements, each processor element having data inputs for receiving digital picture samples, instruction inputs for receiving the instructions and data outputs for generating digital picture samples, each processor element executing instructions converting digital picture samples into processed digital picture samples in accordance with the corresponding control code and register address, each instruction consisting of a control code and a register address, the control code of at least one instruction indicating that instruction is a repeat instruction, an instruction generator circuit including an instruction program memory having a plurality of instructions stored in addressable memory locations, said instruction program memory supplying an instruction including the control code and the register address at an instruction output in response to receipt of a corresponding address at an address input, a program counter connected to said address input of said instruction program memory and having a mode input receiving the operating mode signals from the external source, said program counter supplying an address to said address input of said instruction program memory corresponding to the received operation mode signal, a control code latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the control code of an instruction recalled from said instruction program memory and supplying the control code stored therein to the video signal processing device, a register address latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the register address of an instruction recalled from said instruction program memory and supplying the register address stored therein to the video signal processing device, an instruction decoder circuit connected to said instruction output of said instruction program memory, said control code latch and said register address latch, said instruction decoder circuit for controlling said control code latch to again supply said control code stored therein to the video signal processing device and controlling said register address latch to increment the register address stored therein and supply the incremented register address to the video signal processing device upon detection that the control code of said instruction recalled from said instruction program memory indicates a repeat instruction; a digital to analog converter connected to said processor system for converting said processed digital picture samples into an analog picture signal; a display unit connected to said digital to analog converter for generating a visual display corresponding to said analog picture signal.

Claim 11

A video system comprising: a video signal receiver for generating a picture signal: a controller capable of generating mode signals; and a processor system having an input connected to said video signal receiver for receiving said picture signal, an output for generating a processed picture signal, said processor system including a plurality of one-bit parallel operating processor elements, each processor element having data inputs for receiving picture signals, instruction inputs for receiving the instructions and data outputs for generating processed picture signals, each processor element executing instructions converting picture signals into processed picture signals in accordance with the corresponding control code and register address, each instruction consisting of a control code and a register address, the control code of at least one instruction indicating that instruction is a repeat instruction, an instruction generator circuit including an instruction program memory having a plurality of instructions stored in addressable memory locations, said instruction program memory supplying an instruction including the control code and the register address at an instruction output in response to receipt of a corresponding address at an address input, a program counter connected to said address input of said instruction program memory and having a mode input receiving the operating mode signals from the external source, said program counter supplying an address to said address input of said instruction program memory corresponding to the received operation mode signal, a control code latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the control code of an instruction recalled from said instruction program memory and supplying the control code stored therein to the video signal processing device, a register address latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the register address of an instruction recalled from said instruction program memory and supplying the register address stored therein to the video signal processing device, an instruction decoder circuit connected to said instruction output of said instruction program memory, said control code latch and said register address latch, said instruction decoder circuit for controlling said control code latch to again supply said control code stored therein to the video signal processing device and controlling said register address latch to increment the register address stored therein and supply the incremented register address to the video signal processing device upon detection that the control code of said instruction recalled from said instruction program memory indicates a repeat instruction; and a video display connected to said processor system for forming a visual display corresponding to said processed picture signal.

Claim 12

A video system comprising: a video signal receiver for generating a picture signal: a controller capable of generating mode signals; and a processor system having an input connected to said video signal receiver for receiving said picture signal, an output for generating a processed picture signal, said processor system including a plurality of one-bit parallel operating processor elements, each processor element having data inputs for receiving picture signals, instruction inputs for receiving the instructions and data outputs for generating processed picture signals, each processor element executing instructions converting picture signals into processed picture signals in accordance with the corresponding control code and register address, each instruction consisting of a control code and a register address, the control code of at least one instruction indicating that instruction is a repeat instruction, an instruction generator circuit including an instruction program memory having a plurality of instructions stored in addressable memory locations, said instruction program memory supplying an instruction including the control code and the register address at an instruction output in response to receipt of a corresponding address at an address input, a program counter connected to said address input of said instruction program memory and having a mode input receiving the operating mode signals from the external source, said program counter supplying an address to said address input of said instruction program memory corresponding to the received operation mode signal, a control code latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the control code of an instruction recalled from said instruction program memory and supplying the control code stored therein to the video signal processing device, a register address latch having an input connected to said instruction output of said instruction program memory and an output connected to the video signal processing device for temporarily storing the register address of an instruction recalled from said instruction program memory and supplying the register address stored therein to the video signal processing device, an instruction decoder circuit connected to said instruction output of said instruction program memory, said control code latch and said register address latch, said instruction decoder circuit for controlling said control code latch to again supply said control code stored therein to the video signal processing device and controlling said register address latch to increment the register address stored therein and supply the incremented register address to the video signal processing device upon detection that the control code of said instruction recalled from said instruction program memory indicates a repeat instruction; and a video display connected to said processor system for forming a visual display corresponding to said processed picture signal.