Data unpacker using a pack ratio control signal for unpacked parallel fixed m-bit width into parallel variable n-bit width word

Claim 1

An apparatus for unpacking data, receiving packed parallel data words having a width equal to a fixed number of m valid data bits, and providing parallel output data words having a width equal to a variable number of n valid data bits, where n, m are positive integers, comprising: input register means for receiving and storing said packed parallel data words in a received order, wherein said input register means comprises respective parallel m-bit registers connected in a pipeline, each said parallel m-bit registers storing one said packed parallel data word, respective parallel outputs of each m-bit register being coupled to respective parallel inputs of a consecutive register in said pipeline, and the respective parallel outputs of all said m-bit registers being coupled to respective parallel inputs of a bit shifter means; said bit shifter means for shifting said packed parallel data words from said input register means by a number of bit positions indicated by a shift control signal to provide an n-bit wide parallel output data word; said apparatus further receiving a pack ratio control signal corresponding to a binary representation of said positive integer n for each of said parallel output data words, said pack ratio having a most significant bit (MSB) portion when said positive integer n is equal to or greater than said positive integer m, and at least significant bit (LSB) portion, corresponding to least significant bits of said positive integer n, said MSB portion being applied as a first MSB control signal; adder means for receiving and summing subsequently received LSB portions of said pack ratio control signal to provide a running sum, and for providing a second MSB control signal when said running sum is equal to or greater than said positive integer m, said adder means further providing said shift control signal corresponding to an LSB portion of said running sum; and a logic circuit receiving said first and second MSB control signal, and in response to either of these signals, for providing a ready for data control signal indicating that said input register is ready to receive a packed parallel data word, and a data valid out control signal indicating that said bit shifter means is ready to output said parallel output data word.

Claim 2

An apparatus for unpacking data, receiving packed parallel data words having a width equal to a fixed number of m valid data bits, and providing parallel output data words having a width equal to a variable number of n valid data bits, where n, m are positive integers, comprising: input register means for receiving and storing said packed parallel data words in a received order, wherein said input register means comprises respective parallel m-bit registers connected in a pipeline, each said parallel m-bit registers storing one said packed parallel data word, respective parallel outputs of each m-bit register being coupled to respective parallel inputs of a consecutive register in said pipeline, and the respective parallel outputs of all said m-bit registers being coupled to respective parallel inputs of a bit shifter means; said bit shifter means for shifting said packed parallel data words from said input register means by a number of bit positions indicated by a shift control signal to provide an n-bit wide parallel output data word; said apparatus further receiving a pack ratio control signal corresponding to a binary representation of said positive integer n for each of said parallel output data words, said pack ratio having a most significant bit (MSB) portion when said positive integer n is equal to or greater than said positive integer m, and at least significant bit (LSB) portion, corresponding to least significant bits of said positive integer n, said MSB portion being applied as a first MSB control signal; adder means for receiving and summing subsequently received LSB portions of said pack ratio control signal to provide a running sum, and for providing a second MSB control signal when said running sum is equal to or greater than said positive integer m, said adder means further providing said shift control signal corresponding to an LSB portion of said running sum; and a logic circuit receiving said first and second MSB control signal, and in response to either of these signals, for providing a ready for data control signal indicating that said input register is ready to receive a packed parallel data word, and a data valid out control signal indicating that said bit shifter means is ready to output said parallel output data word.

Claim 9

An apparatus for unpacking data, receiving packed parallel data words having a width equal to a fixed number of m valid data bits, and providing parallel output data words having a width equal to a variable number of n valid data bits, where n, m are positive integers, comprising: input register means for receiving and storing said packed parallel data words in a received order; bit shifter means for shifting said packed parallel data words from said input register means by a number of bit positions indicated by a shift control signal to provide an n-bit wide parallel output data word; said apparatus further receiving a pack ratio control signal corresponding to a binary representation of said positive integer n for each of said parallel output data words, said pack ratio having a most significant bit (MSB) portion when said positive integer n is equal to or greater than said positive integer m, and a least significant bit LSB portion, corresponding to least significant bits of said positive integer n, said MSB portion being applied as a first MSB control signal; adder means for receiving and summing subsequently received LSB portions of said pack ratio control signal to provide a running sum, and for providing a second MSB control signal when said running sum is equal to or greater than said positive integer m, said adder means further providing said shift control signal corresponding to an LSB portion of said running sum; a logic circuit receiving said first and second MSB control signal, and in response to either of these signals, for providing a ready for data control signal indicating that said input register is ready to receive a packed parallel data word, and a data valid out control signal indicating that said bit shifter means is ready to output said parallel output data word; and wherein in response to said ready for data control signal said logic circuit further receives a data valid in control signal indicating that said received packed parallel data words are valid, and enabling input of said valid data words into said input register means, and in response to an absence of said data valid in control signal said logic circuit providing an inhibit control signal to inhibit output of said parallel data words from said bit shifter means, inhibit receipt of a subsequent pack ratio control signal, and inhibit a change in said shift control signal.

Claim 10

An apparatus for unpacking data, receiving packed parallel data words having a width equal to a fixed number of m valid data bits, and providing parallel output data words having a width equal to a variable number of n valid data bits, where n, m are positive integers, comprising: input register means for receiving and storing said packed parallel data words in a received order; bit shifter means for shifting said packed parallel data words from said input register means by a number of bit positions indicated by a shift control signal to provide an n-bit wide parallel output data word; said apparatus further receiving a pack ratio control signal corresponding to a binary representation of said positive integer n for each of said parallel output data words, said pack ratio having a most significant bit (MSB) portion when said positive integer n is equal to or greater than said positive integer m, and a least significant bit LSB portion, corresponding to least significant bits of said positive integer n, said MSB portion being applied as a first MSB control signal; adder means for receiving and summing subsequently received LSB portions of said pack ratio control signal to provide a running sum, and for providing a second MSB control signal when said running sum is equal to or greater than said positive integer m, said adder means further providing said shift control signal corresponding to an LSB portion of said running sum; a logic circuit receiving said first and second MSB control signal, and in response to either of these signals, for providing a ready for data control signal indicating that said input register is ready to receive a packed parallel data word, and a data valid out control signal indicating that said bit shifter means is ready to output said parallel output data word; and wherein in response to said ready for data control signal said logic circuit further receives a data valid in control signal indicating that said received packed parallel data words are valid, and enabling input of said valid data words into said input register means, and in response to an absence of said data valid in control signal said logic circuit providing an inhibit control signal to inhibit output of said parallel data words from said bit shifter means, inhibit receipt of a subsequent pack ratio control signal, and inhibit a change in said shift control signal.

Claim 11

An apparatus for unpacking data, receiving packed parallel data words having a width equal to a fixed number of m valid data bits, variable number of n valid data bits, wherein n, m are positive integers and is equal to or greater than m, comprising: input register means for receiving and storing said packed parallel data words in a received order, wherein said input register means comprises respective parallel m-bit registers connected in a pipeline, each said parallel m-bit registers storing one said packed parallel data word, respective parallel outputs of each m-bit register being coupled to respective parallel inputs of a consecutive register in said m-bit registers being coupled to respective parallel inputs of a bit shifter means; said bit shifter means for shifting said packed parallel data words from said input register means by a number of bit positions indicated by a shift control signal to provide an n-bit wide parallel output data word; said apparatus further receiving a pack ratio control signal corresponding to a binary representation of said positive integer n for each of said parallel output data words, said pack ratio having a most significant bit (MSB) portion and a least significant bit (LSB) portion corresponding to least significant bits of said positive integer n; adder means for receiving and summing subsequently received LSB portions of pack ratio control signal to provide a running sum, and for providing an MSB control signal when said running sum is equal to or greater than said positive integer m, said adder means further providing said shift control signal corresponding to an LSB portion of said running sum; and a logic circuit for receiving said MSB control signal, and in response to the MSB control signal, for providing a data valid out control signal indicating that said bit shifter means is ready to output said parallel output data word.

Claim 12

An apparatus for unpacking data, receiving packed parallel data words having a width equal to a fixed number of m valid data bits, variable number of n valid data bits, wherein n, m are positive integers and is equal to or greater than m, comprising: input register means for receiving and storing said packed parallel data words in a received order, wherein said input register means comprises respective parallel m-bit registers connected in a pipeline, each said parallel m-bit registers storing one said packed parallel data word, respective parallel outputs of each m-bit register being coupled to respective parallel inputs of a consecutive register in said m-bit registers being coupled to respective parallel inputs of a bit shifter means; said bit shifter means for shifting said packed parallel data words from said input register means by a number of bit positions indicated by a shift control signal to provide an n-bit wide parallel output data word; said apparatus further receiving a pack ratio control signal corresponding to a binary representation of said positive integer n for each of said parallel output data words, said pack ratio having a most significant bit (MSB) portion and a least significant bit (LSB) portion corresponding to least significant bits of said positive integer n; adder means for receiving and summing subsequently received LSB portions of pack ratio control signal to provide a running sum, and for providing an MSB control signal when said running sum is equal to or greater than said positive integer m, said adder means further providing said shift control signal corresponding to an LSB portion of said running sum; and a logic circuit for receiving said MSB control signal, and in response to the MSB control signal, for providing a data valid out control signal indicating that said bit shifter means is ready to output said parallel output data word.

Claim 13

An apparatus for unpacking data, receiving packed parallel data words having a width equal to a fixed number of m valid data bits, and providing parallel output data words having a width equal to a variable number of n valid data bits, wherein n, m are positive integers and n is equal to or less than m, comprising: input register means for receiving and storing said packed parallel data words in a received order, wherein said input register means comprises respective parallel m-bit registers connected in a pipeline, each said parallel m-bit register storing one said packed parallel data word, respective parallel outputs of each m-bit register being coupled to respective parallel inputs of a consecutive register in said pipeline, and the respective parallel outputs of all said m-bit registers being coupled to respective parallel inputs of a bit shifter means; said bit shifter means for shifting said packed parallel data words from said input register means by a number of bit positions indicated by a shift control signal to provide an n-bit wide parallel output data word; said apparatus further receiving a pack ratio control signal corresponding to a binary representation of said positive integer n for each of said parallel output data words, said pack ratio having a most significant bit (MSB) portion when said positive integer n equals said positive integer m, and a least significant bit (LSB) portion corresponding to least significant bits of said positive integer n, said MSB portion being applied as a first MSB control signal; adder means for receiving and summing subsequently received LSB portions of said pack ratio control signal to provide a running sum, and for providing a second MSB control signal when said running sum is equal to or greater than said positive integer m, said adder means further providing said shift control signal corresponding to an LSB portion of said running sum; and a logic circuit for receiving said MSB control signal, and in response to the MSB control signal, for providing a data valid out control signal indicating that said bit shifter means is ready to output said parallel output data word.

Claim 14

An apparatus for unpacking data, receiving packed parallel data words having a width equal to a fixed number of m valid data bits, and providing parallel output data words having a width equal to a variable number of n valid data bits, wherein n, m are positive integers and n is equal to or less than m, comprising: input register means for receiving and storing said packed parallel data words in a received order, wherein said input register means comprises respective parallel m-bit registers connected in a pipeline, each said parallel m-bit register storing one said packed parallel data word, respective parallel outputs of each m-bit register being coupled to respective parallel inputs of a consecutive register in said pipeline, and the respective parallel outputs of all said m-bit registers being coupled to respective parallel inputs of a bit shifter means; said bit shifter means for shifting said packed parallel data words from said input register means by a number of bit positions indicated by a shift control signal to provide an n-bit wide parallel output data word; said apparatus further receiving a pack ratio control signal corresponding to a binary representation of said positive integer n for each of said parallel output data words, said pack ratio having a most significant bit (MSB) portion when said positive integer n equals said positive integer m, and a least significant bit (LSB) portion corresponding to least significant bits of said positive integer n, said MSB portion being applied as a first MSB control signal; adder means for receiving and summing subsequently received LSB portions of said pack ratio control signal to provide a running sum, and for providing a second MSB control signal when said running sum is equal to or greater than said positive integer m, said adder means further providing said shift control signal corresponding to an LSB portion of said running sum; and a logic circuit for receiving said MSB control signal, and in response to the MSB control signal, for providing a data valid out control signal indicating that said bit shifter means is ready to output said parallel output data word.