Patent US5239191A successfully refreshed from Google Patents.
US5239191A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor wafer
Assignee: Toshiba Corp
•
Filing: 1992-05-27
•
Granted: 1993-08-24
•
Expires: 2012-05-27
Abstract
Abstract Upon the making of a die-sort testing for a predetermined IC pattern formed on each chip area, a plurality of sets of output pads selectively supplied with output signals are formed on the chip area and connected with a connection pattern on a dicing line area, and one testing pad is provided for the respective set of the pads. The IC patterns are tested by electrically contacting the testing pad with corresponding probe needle of probe card in a die-sort machine.
Inventors
- 👤 Aiichiro Sakumoto
- 👤 Michihiro Kawakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:59
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
113 words
A semiconductor wafer comprising: a plurality of chip areas which are divided by a dicing line area, the plurality of chip areas each having a plurality of bonding pads provided therein; a plurality of connection patterns formed on the dicing line area, each of the plurality of connection patterns connecting the plurality of bonding pads of a corresponding chip area; and a plurality of testing pads, having a predetermined pitch and width, entirely formed on the dicing line area and each respectively connected to a corresponding one of the plurality of connection patterns, the plurality of connection patterns and the plurality of testing pads encompassing substantially the entirety of the dicing line area.
Claim 2
Dependent Claim
113 words
A semiconductor wafer comprising: a plurality of chip areas which are divided by a dicing line area, the plurality of chip areas each having a plurality of bonding pads provided therein; a plurality of connection patterns formed on the dicing line area, each of the plurality of connection patterns connecting the plurality of bonding pads of a corresponding chip area; and a plurality of testing pads, having a predetermined pitch and width, entirely formed on the dicing line area and each respectively connected to a corresponding one of the plurality of connection patterns, the plurality of connection patterns and the plurality of testing pads encompassing substantially the entirety of the dicing line area.
Claim 3
Dependent Claim
51 words
The semiconductor wafer as recited in claim 1 further comprising: an IC pattern, formed on at least one of the plurality of chip areas, including a switching control circuit for selectively supplying output signals to the plurality of bonding pads on the at least one of the plurality of chip areas.
Claim 4
Dependent Claim
31 words
The semiconductor wafer as recited in claim 1, wherein the plurality of testing pads are common testing pads for testing the plurality of bonding pads through the plurality of connection patterns.
Claim 5
Dependent Claim
28 words
The semiconductor wafer as recited in claim 1, wherein each of the plurality of testing pads occupies a larger area than each of the plurality of bonding pads.
Claim 6
Dependent Claim
27 words
The semiconductor wafer as recited in claim 1, wherein a ratio between the plurality of bonding pads and the plurality of test pads is four to one.
Claim 7
Dependent Claim
120 words
A semiconductor wafer comprising: a plurality of chip areas which are divided by a dicing line area, the plurality of chip areas each having a plurality of bonding pads provided thereon; a plurality of connection patterns formed on the dicing line area, each of the plurality of connection patterns connecting the plurality of bonding pads of a corresponding chip area; and a plurality of testing pads, occupying a larger area than each of the plurality of the bonding pads, entirely formed on the dicing line area and each respectively connected to a corresponding one of the plurality of connection patterns, the plurality of connection patterns and the plurality of testing pads encompassing substantially the entirety of the dicing line area.
Claim 8
Dependent Claim
120 words
A semiconductor wafer comprising: a plurality of chip areas which are divided by a dicing line area, the plurality of chip areas each having a plurality of bonding pads provided thereon; a plurality of connection patterns formed on the dicing line area, each of the plurality of connection patterns connecting the plurality of bonding pads of a corresponding chip area; and a plurality of testing pads, occupying a larger area than each of the plurality of the bonding pads, entirely formed on the dicing line area and each respectively connected to a corresponding one of the plurality of connection patterns, the plurality of connection patterns and the plurality of testing pads encompassing substantially the entirety of the dicing line area.
References Cited (Backward Citations)
US3849872A
Cited
US4721995A
Cited
JPS61190950A
Cited
JPS62265731A
Cited
JPS63120434A
Cited
US5003374A
Cited
US5008614A
Cited
US5047711A
Cited
US5032889A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |