SRAM with dual word lines overlapping drive transistor gates

Claim 2

A semiconductor memory device comprising: a semiconductor substrate; element isolation films formed in said semiconductor substrate; active regions formed on said semiconductor substrate, said active regions being defined by said element isolation films; first and second semiconductor strips formed on said element isolation films and over said active regions, each of said first and second semiconductor strips extending in a first direction and having first and second end portions which are separated from each other in said first direction, said first end portions of said first and second semiconductor strips being formed on said element isolation films; memory cells each including first and second transfer MISFETs and cross-coupled first and second inverter circuits, said first inverter circuit having a first drive MISFET and a load element connected in series, said second inverter circuit having a second drive MISFET and a load element connected in series, each of said first and second drive MISFETs having a drain region in said semiconductor substrate, wherein a part of said first semiconductor strip between said first and second end portions of said first semiconductor strip is formed integrally with a gate electrode of said first drive MISFET, and said second end portion of said first semiconductor strip is electrically connected to said drain region of said second drive MISFET, wherein a part of said second semiconductor strip between said first and second end portions of said second semiconductor strip is formed integrally with a gate electrode of said second drive MISFET, and said second end portion of said second semiconductor strip is electrically connected to said drain region of said first drive MISFET; and first and second selecting lines extending in parallel over said semiconductor substrate, said first and second selecting lines extending in a second direction substantially perpendicular to said first direction, wherein each of said memory cells is coupled to both a first and a second selecting line, and wherein gate electrodes of said first and second transfer MISFETs are formed integrally with said first and second selecting lines, respectively, wherein said first selecting lines extend over said first end portions of said second semiconductor strips, and wherein said second selecting lines extend over said first end portions of said first semiconductor strips.

Claim 3

A semiconductor memory device according to claim 1, wherein said first end portions of said first and second semiconductor strips are positioned between said first and second selecting lines which are coupled to the same memory cell.

Claim 4

A semiconductor memory device according to claim 2, wherein said first end portions of said first and second semiconductor strips are positioned between said first and second selecting lines which are coupled to the same memory cell.

Claim 5

A semiconductor memory device according to claim 2, wherein said first and second transfer MISFETs have source and drain regions in said semiconductor substrate, and wherein one of said source and drain regions of said first transfer MISFET is formed integrally with said drain region of said second drive MISFET, one of said source and drain regions of said second transfer MISFET is formed integrally with said drain region of said first drive MISFET, and said drain region of said first drive MISFET is separated from that of said second drive MISFET by said element isolation film.

Claim 6

A semiconductor memory device according to claim 2, wherein said first and second selecting lines are formed of a semiconductor layer which is higher level layer than that of said first and second semiconductor strips.

Claim 7

A semiconductor memroy device according to claim 1, wherein a gate length direction of said first and second transfer MISFETs extends in a direction substantially perpendicular to a gate length direction of said first and second drive MISFETs.

Claim 8

A semiconductor memory device according to claim 1, further comprising: ground potential lines extending in said second direction over said semiconductor substrate and over said first and second semiconductor strips, wherein each said ground potential line is formed with the same conductive layer as that of said first and second selecting lines, wherein each said ground potential line is arranged between said first and second selecting lines which are coupled to the same memory cells, and wherein said ground potential lines are electrically connected to source regions of said first and second drive MISFETs.

Claim 9

A semiconductor device comprising: a semiconductor substrate; element isolation films formed in said semiconductor substrate; active regions formed on said semiconductor substrate, said active regions being defined by said element isolation films; first and second semiconductor strips formed on said element isolation films and over said active regions, each of said first and second semiconductor strips extending in a first direction and having first and second end portions which are separated from each other in said first direction, said first end portions of said first and second semiconductor strips being formed on said element isolation films; memory cells of a static random access memory, each of which includes first and second transfer MISFETs and crosscoupled first and second inverter circuits, said first inverter circuit having a first drive MISFET and a load element connected in series, said second inverter circuit having a second drive MISFET and a load element connected in series, each of said first and second drive MISFETs having a drain region in said semiconductor substrate, wherein a part of said first semiconductor strip between said first and second end portions of said first semiconductor strip is formed integrally with a gate electrode of said first drive MISFETs, and said second end portion of said first semiconductor strip is electrically connected to said drain region of said second drive MISFET, wherein a part of said second semiconductor strip between said first and second end portions of said second semiconductor strip is formed integrally with a gate electrode of said second drive MISFET, and said second end portion of said second semiconductor strip is electrically connected to said drain region of said first drive MISFET, wherein a gate length direction of said first and second transfer MISFETs extends in a direction substantially perpendicular to a gate length direction of said first and second drive MISFETs; first and second selecting lines extending in parallel over said semiconductor substrate, said first and second selecting lines extending in a second direction substantially perpendicular to said first direction, wherein each of said memory cells is coupled to both a first selecting line and a second selecting line, and wherein gate electrodes of said first and second transfer MISFETs are formed integrally with said first and second selecting lines, respectively, wherein said first selecting lines are separated from said second end portions of said first semiconductor strips, and wherein said second selecting lines are separated from said second end portions of said second semiconductor strips, and wherein said first and second selecting lines are formed of a semiconductor layer which is a higher level layer than that of said first and second semiconductor strips; and an insulating film formed on said first and second semiconductor strips, wherein said first selecting lines extend over said first end portions of said second semiconductor strips and on said insulating film, and wherein said second selecting lines extend over said first end portions of said first semiconductor strips and on said insulating film.

Claim 10

A semiconductor device comprising: a semiconductor substrate; element isolation films formed in said semiconductor substrate; active regions formed on said semiconductor substrate, said active regions being defined by said element isolation films; first and second semiconductor strips formed on said element isolation films and over said active regions, each of said first and second semiconductor strips extending in a first direction and having first and second end portions which are separated from each other in said first direction, said first end portions of said first and second semiconductor strips being formed on said element isolation films; memory cells of a static random access memory, each of which includes first and second transfer MISFETs and crosscoupled first and second inverter circuits, said first inverter circuit having a first drive MISFET and a load element connected in series, said second inverter circuit having a second drive MISFET and a load element connected in series, each of said first and second drive MISFETs having a drain region in said semiconductor substrate, wherein a part of said first semiconductor strip between said first and second end portions of said first semiconductor strip is formed integrally with a gate electrode of said first drive MISFETs, and said second end portion of said first semiconductor strip is electrically connected to said drain region of said second drive MISFET, wherein a part of said second semiconductor strip between said first and second end portions of said second semiconductor strip is formed integrally with a gate electrode of said second drive MISFET, and said second end portion of said second semiconductor strip is electrically connected to said drain region of said first drive MISFET, wherein a gate length direction of said first and second transfer MISFETs extends in a direction substantially perpendicular to a gate length direction of said first and second drive MISFETs; first and second selecting lines extending in parallel over said semiconductor substrate, said first and second selecting lines extending in a second direction substantially perpendicular to said first direction, wherein each of said memory cells is coupled to both a first selecting line and a second selecting line, and wherein gate electrodes of said first and second transfer MISFETs are formed integrally with said first and second selecting lines, respectively, wherein said first selecting lines are separated from said second end portions of said first semiconductor strips, and wherein said second selecting lines are separated from said second end portions of said second semiconductor strips, and wherein said first and second selecting lines are formed of a semiconductor layer which is a higher level layer than that of said first and second semiconductor strips; and an insulating film formed on said first and second semiconductor strips, wherein said first selecting lines extend over said first end portions of said second semiconductor strips and on said insulating film, and wherein said second selecting lines extend over said first end portions of said first semiconductor strips and on said insulating film.

Claim 11

A semiconductor device according to claim 8, further comprising: ground potential lines extending in said second direction over said semiconductor substrate and over said first and second semiconductor strips, each of said ground potential lines being formed with the same conductive layer as that of said first and second selecting lines, wherein each said ground potential line is arranged between said first and second selecting lines which are coupled to the same memory cell, wherein said ground potential lines are electrically connected to source regions of said first and second drive MISFETs.

Claim 12

A semiconductor memory device according to claim 1, wherein said memory cells are formed in said active regions.

Claim 13

A semiconductor device according to claim 8, wherein said memory cells are formed in said active regions.