Multi-processor system having a multi-port cache memory

Claim 2

A multi-processor system comprising: a plurality of processors, each having a set of address/data interface signal lines; and a multi-port cache memory shared by said plurality of processors, said cache memory having a plurality of ports, each port being connected to a set of address/data interface signal lines of a respective one of said plurality of processors, and said cache memory also having a plurality of memory cells each being connected to all of said ports and being accessed by all of said plurality of processors by way of said sets of address/data interface signal lines, thereby allowing a read/write operation of each of said memory cells by all of said plurality of processors.

Claim 3

A multi-processor system according to claim 1, wherein said plurality of processors and said multi-port cache memory are fabricated on a single LSI chip.

Claim 4

A multi-processor system comprising: a plurality of processors, each having a first set of address/data interface signal lines for instruction fetch and a second set of address/data interface signal lines for operand fetch; a plurality of instruction cache memories for storing instructions, each of said instruction cache memories being connected to a respective one of said first set of address/data interface lines of said plurality of processors; and a data cache memory shared by said plurality of processors, said data cache memory having a plurality of ports, each port being connected to a second set of address/data interface signal lines of a respective one of said plurality of processors, and said data cache memory also having a plurality of memory cells each being accessed by said plurality of processors by way of said second sets of address/data interface signal lines, thereby allowing a read/write operation of each of said memory cells by said plurality of processors in common.

Claim 5

A multi-processor system comprising: a plurality of processors, each having a first set of address/data interface signal lines for instruction fetch and a second set of address/data interface signal lines for operand fetch; a plurality of instruction cache memories for storing instructions, each of said instruction cache memories being connected to a respective one of said first set of address/data interface lines of said plurality of processors; and a data cache memory shared by said plurality of processors, said data cache memory having a plurality of ports, each port being connected to a second set of address/data interface signal lines of a respective one of said plurality of processors, and said data cache memory also having a plurality of memory cells each being accessed by said plurality of processors by way of said second sets of address/data interface signal lines, thereby allowing a read/write operation of each of said memory cells by said plurality of processors in common.

Claim 6

A multi-processor system according to claim 3, wherein said plurality of processors and said multi-port cache memory are fabricated on a single LSI chip.

Claim 7

A multi-processor system comprising: a plurality of processors, each having a first set of address/data interface signal lines for instruction fetch and a second set of address/data interface signal lines for operand fetch; and a multi-port cache memory shared by said plurality of processors, said cache memory having a plurality of ports, each port being connected to a first set of address/data interface signal lines and a second set of address/data interface signal lines of a respective one of said plurality of processors, and said cache memory also having a plurality of memory cells each being connected to all of said ports and being accessed by said plurality of processors by way of said first and second sets of address/data interface signal lines, thereby allowing a read/write operation of each of said memory cells by plural processors independently of each other between instruction fetch and operand fetch.

Claim 8

A multi-processor system comprising: a plurality of processors, each having a first set of address/data interface signal lines for instruction fetch and a second set of address/data interface signal lines for operand fetch; and a multi-port cache memory shared by said plurality of processors, said cache memory having a plurality of ports, each port being connected to a first set of address/data interface signal lines and a second set of address/data interface signal lines of a respective one of said plurality of processors, and said cache memory also having a plurality of memory cells each being connected to all of said ports and being accessed by said plurality of processors by way of said first and second sets of address/data interface signal lines, thereby allowing a read/write operation of each of said memory cells by plural processors independently of each other between instruction fetch and operand fetch.

Claim 9

A multi-processor system according to claim 5, wherein said plurality of processors and said multi-port cache memory are fabricated on a single LSI chip.

Claim 10

A multi-processor system comprising: a plurality of processors, each processor having a set of address lines and data lines; and a single multi-port cache memory connected to said processors via said sets of address lines and data lines, and having a plurality of memory cells, a plurality of address decoders equal to the number of said processors for addressing said memory cells and a plurality of read/write data lines equal to the number of said processors; wherein each of said address decoders is connected to a respective set of address lines of said plurality of processors; each of said read/write data lines is connected to a set of data lines of a respective one of said plurality of processors; and each of said memory cells is provided with a set of gate means, each gate means being connected to a respective one of said read/write data lines and being on-off controlled by a respective one of said address decoders so as to selectively connect that memory cell to one of said read/write data lines.

Claim 11

A multi-processor system comprising: a plurality of processors, each processor having a set of address lines and data lines; and a single multi-port cache memory connected to said processors via said sets of address lines and data lines, and having a plurality of memory cells, a plurality of address decoders equal to the number of said processors for addressing said memory cells and a plurality of read/write data lines equal to the number of said processors; wherein each of said address decoders is connected to a respective set of address lines of said plurality of processors; each of said read/write data lines is connected to a set of data lines of a respective one of said plurality of processors; and each of said memory cells is provided with a set of gate means, each gate means being connected to a respective one of said read/write data lines and being on-off controlled by a respective one of said address decoders so as to selectively connect that memory cell to one of said read/write data lines.

Claim 12

A multi-processor system comprising: a plurality of processors, each having a first set of address lines and data lines for instruction fetch, and a second set of address lines and data lines for operand fetch; and a single multi-port cache memory having a first set of ports and a second set of ports connected to said first set of address lines and data lines and second set of address lines and data lines, respectively, and also having a plurality of memory cells, a number of address decoders equal to the number of said processors for each set of ports and a number of read/write data lines equal to the number of said processors for each set of ports; wherein each of said address decoders is connected to a respective set of address lines of said plurality of processors for each set of ports; each of said read/write data lines being connected to a set of data lines of a respective one of said plurality of processors for each set of ports; each of said memory cells being addressed by said address decoders for each set of ports; and each of said memory cells for each port being provided with a set of gate means, each gate means being connected to a respective one of said read/write data lines and being on-off controlled by one of said address decoders so as to selectively connect that memory cell to one of said read/write data lines.

Claim 13

A multi-processor system comprising: a plurality of processors, each having a first set of address lines and data lines for instruction fetch, and a second set of address lines and data lines for operand fetch; and a single multi-port cache memory having a first set of ports and a second set of ports connected to said first set of address lines and data lines and second set of address lines and data lines, respectively, and also having a plurality of memory cells, a number of address decoders equal to the number of said processors for each set of ports and a number of read/write data lines equal to the number of said processors for each set of ports; wherein each of said address decoders is connected to a respective set of address lines of said plurality of processors for each set of ports; each of said read/write data lines being connected to a set of data lines of a respective one of said plurality of processors for each set of ports; each of said memory cells being addressed by said address decoders for each set of ports; and each of said memory cells for each port being provided with a set of gate means, each gate means being connected to a respective one of said read/write data lines and being on-off controlled by one of said address decoders so as to selectively connect that memory cell to one of said read/write data lines.

Claim 14

A multi-processor system comprising: a plurality of processors, each having a first set of address lines and data lines for instruction fetch, and a second set of address lines and data lines for operand fetch; a plurality of instruction cache memories for storing instructions, each of said instruction cache memories being connected to each first set of address lines and data lines of said plurality of processors; and a data multi-port cache memory connected to said processors via said second sets of address lines and data lines, and having a plurality of memory cells, a number of address decoders equal to the number of said processors and a number of read/write data lines equal to the number of said processors; wherein each of said address decoders is connected to a respective second set of address lines of said plurality of processors; each of said read/write data lines is connected to a respective second set of data lines of said plurality of processors; each of said memory cells is addressed by said address decoders; and each of said memory cells is provided with a set of gate means, each gate means being connected to a respective one of said read/write data lines and being on-off controlled by one of said address decoders so as to selectively connect that memory cell to one of said read/write data lines.

Claim 15

A multi-processor system comprising: a plurality of processors, each having a first set of address lines and data lines for instruction fetch, and a second set of address lines and data lines for operand fetch; a plurality of instruction cache memories for storing instructions, each of said instruction cache memories being connected to each first set of address lines and data lines of said plurality of processors; and a data multi-port cache memory connected to said processors via said second sets of address lines and data lines, and having a plurality of memory cells, a number of address decoders equal to the number of said processors and a number of read/write data lines equal to the number of said processors; wherein each of said address decoders is connected to a respective second set of address lines of said plurality of processors; each of said read/write data lines is connected to a respective second set of data lines of said plurality of processors; each of said memory cells is addressed by said address decoders; and each of said memory cells is provided with a set of gate means, each gate means being connected to a respective one of said read/write data lines and being on-off controlled by one of said address decoders so as to selectively connect that memory cell to one of said read/write data lines.

Claim 16

A multi-processor system comprising: a plurality of processors, each having a set of address/data interface signal lines; and a single multi-port cache memory for storing a portion of data stored in a main memory and having a number of cells and a plurality of ports each accessible to all of said number of cells, each port being connected to a set of address/data interface signal lines of a respective one of said plurality of processors.

Claim 17

A multi-processor system comprising: a plurality of processors, each having a set of address/data interface signal lines; and a single multi-port cache memory for storing a portion of data stored in a main memory and having a number of cells and a plurality of ports each accessible to all of said number of cells, each port being connected to a set of address/data interface signal lines of a respective one of said plurality of processors.

Claim 18

A multi-processor system according to claim 10, wherein each of said cells of said cache memory is connected to all of said ports.

Claim 19

A multi-processor system comprising: a plurality of processors, each having a first set of address/data interface signal lines for instruction fetch and a second set of address/data interface signal lines for operand fetch; and a single multi-port cache memory for storing both instructions and operand data, said single cache memory having a number of cells and a plurality of ports each accessible to all of said number of cells, each port being connected to a first set of address/data interface signal lines and a second set of address/data interface signal lines of a respective one of said plurality of processors.

Claim 20

A multi-processor system comprising: a plurality of processors, each having a first set of address/data interface signal lines for instruction fetch and a second set of address/data interface signal lines for operand fetch; and a single multi-port cache memory for storing both instructions and operand data, said single cache memory having a number of cells and a plurality of ports each accessible to all of said number of cells, each port being connected to a first set of address/data interface signal lines and a second set of address/data interface signal lines of a respective one of said plurality of processors.

Claim 21

A multi-processor system according to claim 12, wherein each of said cells of said cache memory is connected to all of said ports.

Claim 22

A multi-processor system comprising: a plurality of processors, each having a first set of address lines and data lines for instruction fetch and a second set of address lines and data lines for operand fetch; a plurality of instruction cache memories for storing instructions, each of said instruction cache memories being connected to each first set of address/data interface signal lines of said plurality of processors; and a single multi-port cache memory having a plurality of ports, each port being connected to a second set of address lines and data lines of a respective one of said plurality of processors.

Claim 23

A multi-processor system comprising: a plurality of processors, each having a first set of address lines and data lines for instruction fetch and a second set of address lines and data lines for operand fetch; a plurality of instruction cache memories for storing instructions, each of said instruction cache memories being connected to each first set of address/data interface signal lines of said plurality of processors; and a single multi-port cache memory having a plurality of ports, each port being connected to a second set of address lines and data lines of a respective one of said plurality of processors.