Half-bridge inverter with capacitive voltage equalizer

Claim 2

A half-bridge inverter circuit adapted for converting a DC voltage source to an AC voltage waveform and supplying said AC voltage waveform to a load, wherein said half-bridge inverter circuit includes an inverter means comprising a first capacitor for supplying a positive output voltage relative to a ground voltage during the positive portion of said AC voltage waveform and a second capacitor for supplying a negative output voltage relative to said ground voltage during the negative portion of said AC voltage waveform, said half-bridge inverter circuit comprising: a first control means responsive to the level of said positive output voltage, said negative output voltage, and said ground voltage for selectively charging said first capacitor and said second capacitor, and an equalizer means responsive to said first control means for equalizing said positive output voltage supplied by said first capacitor and said negative output voltage supplied by said second capacitor.

Claim 3

A half-bridge inverter circuit according to claim 1, wherein said inverter means further comprises: an output filter means responsive to said positive output voltage, said negative output voltage, and said ground voltage for generating said AC voltage waveform.

Claim 4

A half-bridge inverter circuit according to claim 2, wherein said half-bridge inverter circuit further comprises: a second control means responsive to said positive output voltage, said negative output voltage, said ground voltage and said AC voltage waverform for controlling said positive output voltage and said negative output voltage.

Claim 5

A half-bridge inverter circuit according to claim 3, wherein said inverter means further comprises: a first inverter switching means responsive to said second control means for providing said positive output voltage to said output filter means, and a second inverter switching means responsive to said second control means for providing said negative output voltage to said output filter means.

Claim 6

A half-bridge inverter circuit according to claim 1, wherein said first capacitor and said second capacitor are connected in series.

Claim 7

A half-bridge inverter circuit according to claim 1, wherein the negative terminal of said first capacitor is connected to the positive terminal of said second capacitor, said negative terminal of said first capacitor and said positive terminal of said second capacitor corresponding to said ground voltage.

Claim 8

A half-bridge inverter circuit according to claim 6, wherein said equalizer means further comprises: a first equalizer switching means responsive to said first control means for selectively coupling said DC voltage source to said second capacitor to charge said second capacitor, and a second equalizer switching means responsive to said first control means for selectively coupling said DC voltage source to said first capacitor to charge said capacitor.

Claim 9

A half-bridge inverter circuit according to claim 7, wherein said equializer means further comprises: a choke means coupled between said first equalizer switching means, said second equalizer switching means, the negative terminal of said first capacitor, and the positive terminal of said second capacitor for providing said ground voltage equal to half of said DC voltage source.

Claim 10

A half-bridge inverter circuit according to claim 7, wherein said first control means comprises: summing means for summing said positive output voltage and said negative output voltage and generating a summed voltage, amplifying means responsive to said summing means for amplifying said summed voltage relative to said ground voltage, pulse width modulating means responsive to said amplifying means for generating a series of pulses, and driver means responsive to said pulse width modulating means for selectively activating said first equalizer switching means and said second equalizer switching means.

Claim 11

A half-bridge inverter circuit according to claim 9, wherein the frequency of said series of pulses is greater than the frequency of said AC voltage waveform.

Claim 12

A half-bridge inverter circuit according to claim 9, wherein the frequency of said series of pulses is 50 times greater than the frequency of said AC voltage waveform.

Claim 13

A half-bridge inverter circuit according to claim 9, wherein said driver means activates said first equalizer switching means during the absence of a pulse of said series of pulses.

Claim 14

A half-bridge inverter circuit according to claim 9, wherein said driver means activates said second equalizer switching means during the presence of a pulse of said series of pulses.

Claim 15

A half-bridge inverter circuit according to claim 9, wherein the duty cycle of said series of pulses varies proportionately responsive to said amplifying means.

Claim 16

A half-bridge inverter circuit according to claim 9, wherein said pulse width modulating means generates said series of pulses with a duty cycle of less than 50% when said summed voltage is less than said ground voltage.

Claim 17

A half-bridge inverter circuit according to claim 9, wherein said pulse width modulating means generates said series of pulses with a duty cycle of greater than 50% when said summed voltage is greater than said ground voltage.

Claim 18

A half-bridge inverter circuit according to claim 9, wherein said pulse width modulating means generates said series of pulses with a duty cycle equal to 50% when said summed voltage is equal to said ground voltage.

Claim 19

A half-bridge inverter circuit according to claim 1, wherein the positive terminal of said DC voltage source is connected to the positive terminal of said first capacitor, the negative terminal of said DC voltage source is connected to the negative terminal of said second capacitor, and the negative terminal of said first capacitor is connected to the positive terminal of said second capacitor, said negative terminal of said first capacitor and said positive terminal of said second capacitor corresponding to said ground voltage, said equalizer means further comprising: a choke coupled between a first node and said ground voltage, a first switch couple between the positive terminal of said DC voltage source and said first node, a second switch coupled between the negative terminal of said DC voltage source and said first node, a first diode coupled between the positive terminal of said DC voltage source and said first node, so as to allow current to flow from said first node to the positive terminal of said DC voltage source, and a second diode coupled between the negative terminal of said DC voltage source and said first node, so as to allow current to flow from the negative terminal of said DC voltage source to said first node.

Claim 20

A half-bridge inverter circuit according to claim 18, wherein said first control means comprises: summing means for summing said positive output voltage and said negative output voltage and generating a summed voltage, amplifying means responsive to said summing means for amplifying said summed voltage relative to said ground voltage, pulse width modulating means responsive to said amplifying means for generating a series of pulses, and driver means responsive to said pulse width modulating means for driving said first switch and said second switch.

Claim 21

A half-bridge inverter circuit adapted for converting a DC voltage source to an AC voltage waveform and supplying said AC voltage waveform to a load, wherein said half-bridge inverter circuit includes an inverter means comprising a first capacitor for supplying a positive output voltage relative to a ground voltage during the positive portion of said AC voltage waveform and a second capacitor for supplying a negative output voltage relative to said ground voltage during the negative portion of said AC voltage waveform, said half-bridge inverter circuit comprising: a first control means responsive to the level of said positive output voltage, said negative output voltage, and said ground voltage for selectively charging said first capacitor and said second capacitor, and an equalizer means responsive to said first control means for equalizing a first output voltage supplied by said first capacitor and a second output voltage supplied by said second capacitor, said equalizer means including a first equalizer switching means responsive to said first control means for selectively coupling said DC voltage source to said second capacitor to charge said second capacitor, and a second equalizer switching means responsive to said first control means for selectively coupling said DC voltage source to said first capacitor to charge said capacitor, said control performing the steps of: (a) summing said positive output voltage and said negative output voltage (b) generating a summed voltage responsive to said summing step, (c) amplifying said summed voltage relative to said ground voltage, (d) pulse width modulating a series of pulses responsive to said amplifying step, and (e) selectively activating said first equalizer switching means and said second equalizer switching means responsive to said pulse width modulating step.

Claim 22

A half-bridge inverter circuit adapted for converting a DC voltage source to an AC voltage waveform and supplying said AC voltage waveform to a load, wherein said half-bridge inverter circuit includes an inverter means comprising a first capacitor for supplying a positive output voltage relative to a ground voltage during the positive portion of said AC voltage waveform and a second capacitor for supplying a negative output voltage relative to said ground voltage during the negative portion of said AC voltage waveform, said half-bridge inverter circuit comprising: a first control means responsive to the level of said positive output voltage, said negative output voltage, and said ground voltage for selectively charging said first capacitor and said second capacitor, and an equalizer means responsive to said first control means for equalizing a first output voltage supplied by said first capacitor and a second output voltage supplied by said second capacitor, said equalizer means including a first equalizer switching means responsive to said first control means for selectively coupling said DC voltage source to said second capacitor to charge said second capacitor, and a second equalizer switching means responsive to said first control means for selectively coupling said DC voltage source to said first capacitor to charge said capacitor, said control performing the steps of: (a) summing said positive output voltage and said negative output voltage (b) generating a summed voltage responsive to said summing step, (c) amplifying said summed voltage relative to said ground voltage, (d) pulse width modulating a series of pulses responsive to said amplifying step, and (e) selectively activating said first equalizer switching means and said second equalizer switching means responsive to said pulse width modulating step.

Claim 23

A half-bridge inverter circuit according to claim 20, wherein the frequency of said series of pulses modulated in said pulse width modulating step is greater than the frequency of said AC voltage waveform.

Claim 24

A half-bridge inverter circuit according to claim 20, wherein the frequency of said series of pulses modulated in said pulse width modulating step is 50 times greater than the frequency of said AC voltage waveform.

Claim 25

A half-bridge inverter circuit according to claim 20, wherein said selective activation step activates said first equalizer switching means during the absence of a pulse of said series of pulses.

Claim 26

A half-bridge inverter circuit according to claim 20, wherein said selective activation step activates said second equalizer switching means during the presence of a pulse of said series of pulses.

Claim 27

A half-bridge inverter circuit according to claim 20, wherein the duty cycle of said series of pulses varies proportionately responsive to said amplifying step.

Claim 28

A half-bridge inverter circuit according to claim 20, wherein said pulse width modulating means generates said series of pulses with a duty cycle of less than 50% when said summed voltage is less than said ground voltage.

Claim 29

A half-bridge inverter circuit according to claim 20, wherein said pulse width modulating means generates said series of pulses with a duty cycle of greater than 50% when said summed voltage is greater than said ground voltage.

Claim 30

A half-bridge inverter circuit according to claim 20, wherein said pulse width modulating means generates said series of pulses with a duty cycle equal to 50% when said summed voltage is equal to said ground voltage.