JJ-MOS read access circuit for MOS memory

Claim 1

An electrical circuit for selecting memory cells in a memory array and reading data contained in a selected memory cell, said memory cells selected by a memory array row and a memory array column, said electrical circuit using superconducing junction devices that are switched between a superconducting and voltage gap mode, said memory cells not using such superconducting junction devices, said circuit comprising: a first superconducting junction device for selecting a memory array row; a second superconducting device for selecting a memory array column; third and fourth superconducting devices each having a control loop for modifying the amount of critical current required to switch modes; a fifth superconducting device having first and second control loops, wherein the difference between the currents in said first and second control loops controls the amount of critical current required to switch modes in said fifth junction device; first clock means connected to said first junction, said first clock means having a current signal that switches said first junction into the voltage gap mode thereby generating a memory array row select signal; means for providing the row select signal to said third junction device control loop when the memory cell contains a logic one and to said fourth junction device control loop when the memory cell contains a logic zero; means for providing the output voltage of said third and fourth devices as an input control signal to said first and second control loops of said fifth junction device, respectively; second clock means connected to said second junction, said second clock means having a current signal that switches said second junction into the voltage gap mode thereby generating a memory array column select signal; means for providing the column select signal to said third and fourth junction devices, wherein the column select signal switches said third or fourth junction into the voltage gap mode when the respective control loop is connected to the row select signal; and third clock means connected to said fifth junction, said third clock means having a current signal that switches said fifth junction into the voltage gap mode when the current resulting from the column select signal is less in the first control loop than in the second control loop of said fifth junction, causing the data contents of the memory cell to be presented at the fifth junction mode.