Patent US5256274A successfully refreshed from Google Patents.
US5256274A
Expired / Lapsed
US
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Selective metal electrodeposition process
Assignee: Individual
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Filing: 1991-11-22
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Granted: 1993-10-26
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Expires: 2011-11-22
Abstract
Abstract A process and apparatus for advanced semiconductor applications which involves the selective electrodeposition of metal on a semiconductor wafer is described. The present invention has significant economic and performance advantages over the current state of the art. It addresses problems associated with cleanliness (a major issue with sub-micron processing) , metal thickness uniformity, step coverage and environmental concerns. A metal with better device performance capabilities compared to the standard aluminum is also employed. The hardware allows the selective deposition to occur without allowing the electrolyte to contact the rear of the wafer or the electrodes contacting the front wafer surface. A virtual anode improves the primary current distribution improving the thickness uniformity while allowing optimization of other film parameters with the remaining deposition variables. Using this process and the associated hardware, metal lines are selectively deposited with contacts or vias completely filled without the need for plasma etching the deposited metal.
Inventors
- 👤 Jaime Poris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:29
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10P; H10P14/00; H10P14/40; H10P14/46; H10P14/47
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
129 words
A wafer level sub micron interconnect metallization process for electrodeposition of metal such as copper, silver or gold onto a semiconductor wafer having an active layer such as silicon, said process comprising the steps of depositing an electrically conducting layer on said wafer having contacts and vias, to prevent metal diffusion to said silicon, and to provide a sufficient adhesion surface for the electrodeposited metal, placing, using an inert photoresist metal mask process, a first metal mask layer onto said wafer, selectively depositing said metal onto said conducting layer of said semiconducting wafer to form one or more lines, removing said first metal mask layer from said wafer, and electrochemically etching to increase a radius of curvature of edges of said lines, thereby facilitating planarization and decreasing line-to-line capacitance.
Claim 2
Dependent Claim
129 words
A wafer level sub micron interconnect metallization process for electrodeposition of metal such as copper, silver or gold onto a semiconductor wafer having an active layer such as silicon, said process comprising the steps of depositing an electrically conducting layer on said wafer having contacts and vias, to prevent metal diffusion to said silicon, and to provide a sufficient adhesion surface for the electrodeposited metal, placing, using an inert photoresist metal mask process, a first metal mask layer onto said wafer, selectively depositing said metal onto said conducting layer of said semiconducting wafer to form one or more lines, removing said first metal mask layer from said wafer, and electrochemically etching to increase a radius of curvature of edges of said lines, thereby facilitating planarization and decreasing line-to-line capacitance.
Claim 3
Dependent Claim
28 words
The method of claim 1 including the step of forming heat sink layers between one or more active metal layers or as ground planes between said metal layers.
Claim 4
Dependent Claim
191 words
A wafer level sub micron interconnect metallization process for electrodeposition of metal such as copper, silver or gold onto a semiconductor wafer having an active layer such as silicon, said process comprising the steps of providing a semiconductor wafer with active device semiconductor, depositing, using a diffusion barrier deposition process, an electrically conducting layer on said wafer to provide adequate adhesion to said wafer, to provide ohmic contact to said wafer and to prevent metal diffusion to said active device semiconductor or other semiconductor areas of said wafer, depositing, using an electrically conducting nucleation layer deposition process, an ohmic contact to diffusion barrier layer which provides a sufficient adhesion surface and nucleation surface for the electrodeposited metal, placing a non-conducting mask onto said diffusion barrier/nucleation layer on said semiconductor wafer, selectively depositing said metal onto said diffusion barrier/nucleation layer on said semiconductor wafer to form one or more lines having corners and edges, removing the non-conducting mask while not adversely affecting the electrodeposited metal, and electrochemically etching to increase a radius of curvature of the corners and edges of metal lines to simplify planarization processing and decrease line to line capacitance.
Claim 5
Dependent Claim
191 words
A wafer level sub micron interconnect metallization process for electrodeposition of metal such as copper, silver or gold onto a semiconductor wafer having an active layer such as silicon, said process comprising the steps of providing a semiconductor wafer with active device semiconductor, depositing, using a diffusion barrier deposition process, an electrically conducting layer on said wafer to provide adequate adhesion to said wafer, to provide ohmic contact to said wafer and to prevent metal diffusion to said active device semiconductor or other semiconductor areas of said wafer, depositing, using an electrically conducting nucleation layer deposition process, an ohmic contact to diffusion barrier layer which provides a sufficient adhesion surface and nucleation surface for the electrodeposited metal, placing a non-conducting mask onto said diffusion barrier/nucleation layer on said semiconductor wafer, selectively depositing said metal onto said diffusion barrier/nucleation layer on said semiconductor wafer to form one or more lines having corners and edges, removing the non-conducting mask while not adversely affecting the electrodeposited metal, and electrochemically etching to increase a radius of curvature of the corners and edges of metal lines to simplify planarization processing and decrease line to line capacitance.
Claim 6
Dependent Claim
67 words
The method of claim 3 wherein the diffusion barrier has an approximate thickness of 1000 Angstroms and is one of the following: A) titanium sputter deposition rapid thermal nitridation (with nitrogen or ammonia) to form titanium nitride B) reactively sputtered titanium nitride C) low pressure chemical vapor deposition (LPCVD) titanium nitride or titanium-tungsten instead of titanium, and titanium-tungsten nitride instead of titanium nitride, in A) and B).
Claim 7
Dependent Claim
49 words
The method of claim 3 wherein the nucleation layer is one of the following: A) sputtered platinum, iridium, osmium, or palladium having an approximate thickness of 250 Angstroms B) a chemically treated diffusion barrier, said chemically treated diffusion barrier providing a surface for adequate nucleation of the electrodeposited metal.
Claim 8
Dependent Claim
13 words
The method of claim 3 wherein the electrodeposition process uses copper or silver.
Claim 9
Dependent Claim
22 words
The method of claim 1 wherein said selective electrodeposition process simultaneously fills one or more contacts or vias while forming said lines.
Claim 10
Dependent Claim
63 words
The method of claim 3, further comprising a dielectric deposition process to provide adequate adhesion to the electrodeposited metal and act as a diffusion barrier to prevent the electrodeposited metal from diffusion in a major constituent of the dielectric layer, each of the vias having a bottom, and a dielectric via process to expose the electrodeposited metal at the bottom of the vias.
Claim 11
Dependent Claim
22 words
The method of claim 8 wherein said selective electrodeposition process simultaneously fills one or more contacts or vias while forming said lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-25 | 1997-04-26 | 1997-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-25 | 2001-04-26 | 2001-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-25 | 2005-04-26 | 2005-10-26 | $7700.00 | Window Closed / Lapsed |