π/4 differential encoding for digital cellular mobile systems

Claim 2

A π/4 differential phase shift encoder comprising: serial-to-parallel converter means for converting an input binary data stream, b m , into first and second data sequences X k and Y k ; first logic means for receiving said data sequences X k and Y k and generating a 3-bit binary code; adder means for receiving as a first input the 3-bit binary code generated by said first logic means and producing a 3-bit sum output; delay means for delaying said 3-bit sum output and providing the delayed 3-bit sum output to a second input of said adder means; and table lookup means receiving said 3-bit sum output as an address and outputting signals, I k and Q k , according to a second table, said signals I k and Q k being defined according to the following equations: I.sub.k =I.sub.k-1 cos (DP(X.sub.k,Y.sub.k))-Q.sub.k-1 sin (DP(X.sub.k,Y.sub.k)) (3) Q.sub.k =I.sub.k-1 sin (DP(X.sub.k,Y.sub.k))+Q.sub.k-1 cos (DP(X.sub.k,Y.sub.k)) (4) where I k-1 and Q k-1 are the amplitudes at the previous pulse time and DP is the differential phase.

Claim 3

The π/4 differential phase shift encoder recited in claim 1 wherein said 3-bit binary code is defined according to a first table as ______________________________________ X.sub.k Y.sub.k PHASE CHANGE ______________________________________ 0 0 001 0 1 011 1 0 111 1 1 101 ______________________________________ and wherein said signals, I k and Q k , are defined according to a second table as ______________________________________ STATE VALUE I.sub.k Q.sub.k ______________________________________ 000 0.0 -1.0 001 ##STR9## ##STR10## 010 -1.0 0.0 011 ##STR11## ##STR12## 100 0.0 +1.0 101 ##STR13## ##STR14## 110 1.0 0.0 111 ##STR15## ##STR16## ______________________________________

Claim 4

A process implemented on a microprocessor for generating π/ 4 differential phase shift encoding comprising the steps of: receiving an input binary data stream to be encoded and outputting first and second data sequences X k and Y k from a serial to parallel converter; accessing a first lookup table to determine the differential phase value, DP k ; calculating a new state, TEMP, as TEMP=S k-1 +DP k ; applying modulo 8 to the new state as S k =TEMP·AND·7; determining the analog values for I and Q amplitudes by accessing a second lookup table; and repeating the process for all the data to be encoded.

Claim 5

A process implemented on a microprocessor for generating π/ 4 differential phase shift encoding comprising the steps of: receiving an input binary data stream to be encoded and outputting first and second data sequences X k and Y k from a serial to parallel converter; accessing a first lookup table to determine the differential phase value, DP k ; calculating a new state, TEMP, as TEMP=S k-1 +DP k ; applying modulo 8 to the new state as S k =TEMP·AND·7; determining the analog values for I and Q amplitudes by accessing a second lookup table; and repeating the process for all the data to be encoded.

Claim 6

The process for generating π/4 differential phase shift encoding recited in claim 3 wherein said first table is defined as ______________________________________ X.sub.k Y.sub.k PHASE CHANGE ______________________________________ 0 0 001 0 1 011 1 0 111 1 1 101 ______________________________________ and wherein said second table is defined as ______________________________________ STATE VALUE I.sub.k Q.sub.k ______________________________________ 000 0.0 -1.0 001 ##STR17## ##STR18## 010 -1.0 0.0 011 ##STR19## ##STR20## 100 0.0 +1.0 101 ##STR21## ##STR22## 110 +1.0 0.0 111 ##STR23## ##STR24## ______________________________________