Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices

Claim 1

In a computer system including a central processing unit (CPU), a main memory, a plurality of input/output (I/O) devices, and an operating system, wherein said I/O devices transfer data directly between said I/O devices and said main memory without being under the control of said CPU, an I/O cache for caching said I/O data being transferred between said I/O devices and said main memory, said I/O cache comprising: a) I/O cache data array means coupled to said main memory, said CPU, said I/O devices including a first and a second plurality of I/O cache lines for caching a first and second subset of said I/O data, said first and second subsets of said I/O data being transferred directly between said main memory and I/O devices of a first and a second type respectively, said I/O devices being classified by said operating system into at least a first and a second types, each I/O cache line of said first plurality of I/O cache lines being mapped to a memory page of said main memory allocated to an I/O device of said first type, each of said I/O devices of said first type being allocated at least one I/O cache mapped memory page dynamically by said operating system, each I/O cache line of said second plurality of I/O cache lines being grouped with at least one other I/O cache line of said second plurality of I/O cache lines, each group of I/O cache lines of said second plurality of I/O cache lines being mapped to a plurality of memory pages of said main memory allocated to an I/O device of said second type, each of said I/O devices of said second type being allocated a plurality of I/O cache mapped memory pages statically by said operating system; b) I/O cache tag array means coupled to said CPU and said I/O devices including a plurality of I/O tag entries for storing addresses and associated control information for said first and second plurality of I/O cache lines, each of said I/O tag entries having at least one I/O tag, each of said I/O tags storing an address and associated control information for one of said first and second plurality of I/O cache lines; c) I/O mapper means coupled to said CPU and said I/O devices including a plurality of indicators corresponding to memory pages of said main memory for indicating I/O cacheability of said corresponding memory pages, each caheability indicator corresponding to one of said I/O cache mapped memory pages allocated to one of said I/O devices of said first and second types being marked cacheable by said operating system upon allocating the specific memory page to the I/O device of said first and second types; and d) I/O control logic means coupled to said CPU, said I/O devices, said I/O cache data array means, said I/O cache tag array means, and said I/O cache mapper means for arbitrating accesses by said CPU and said I/O devices to said I/O cache data array means, said I/O cache tag array means and I/O cache mapper means, and controlling said I/O cache data array means, said I/O cache tag array means and I/O cache mapper means.